Datasheet

TLK2541
SLLS779B –JANUARY 2008–REVISED APRIL 2008 www.ti.com
TERMINAL FUNCTIONS
TERMINAL
TYPE DESCRIPTION
NAME NO.
Serial Transmit Outputs. DOUTTXP and DOUTTXN are differential serial outputs that
interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of
DOUTTXP 72 Output
10 or 20 times the TX_CLK value. DOUTTXP and DOUTTXN are put in a high impedance
DOUTTXN 71 (Hi-Z power-up)
state when LOOPEN is high and are active when LOOPEN is low. When Disabled or
during power-on-reset these pins are high impedance.
DINRXP 67 Serial Receive Inputs. DINRXP and DINRXN together are the differential serial input
Input
DINRXN 66 interface from a copper or an optical I/F module.
Transmit Clock. TX_CLK is a continuous external input clock that synchronizes the
transmitter parallel interface signals TXD[0:19]. The frequency range of TX_CLK is 100
TX_CLK 10 Input
MHz to 130 MHz. The transmitter uses the rising edge of this clock to register the input
data (TXD) for serialization.
Reference Clock. REFCLK is a clean reference clock for input to the phase lock loop.
REFCLK 75 Input
REFCLK must be the same frequency as TX_CLK.
TXD0 78 Transmit Data Bus. These inputs carry the 20-bit parallel data output from a protocol
TXD1 79 device to the transceiver for serialization and transmission. This 20-bit parallel data is
TXD2 1 clocked into the transceiver on the rising edge of TX_CLK.
TXD3 3
When the transmitter is operating at 20 times REFCLK rate, the full width of the transmit
TXD4 4
parallel bus is latched on the rising edge of TX_CLK and serialized. When the transmitter
TXD5 5
is operating at 10 times REFCLK rate, only the lower half of the transmit parallel bus is
TXD6 6
latched and serialized.
TXD7 8
When the on-chip encode/decode logic is bypassed, the full 20 bit data bus is serialized at
TXD8 9
full data rate. At half data rate only bits TXD0 through TXD9 are serialized.
TXD9 12
Input
TXD10 13
When the on-chip encode/decode logic is utilized, bits TXD[0:7] make up the lower order
TXD11 14
data byte and bit TXD[16] becomes the K control bit for the lower order byte. Bits
TXD12 16
TXD[8:15] make up the higher order byte and bit TXD[17] becomes the K control bit for the
TXD13 17
higher order byte. Bits TXD[18] and TXD[19] are ignored. At full data rate both lower and
TXD14 18
higher order bytes are latched, coded, and serialized. At half data rate, only the lower order
TXD15 19
byte is latched, coded and serialized.
TXD16 21
TXD17 23
The lower order byte is always serialized first, and the lower order bit in a byte is always
TXD18 24
serialized first.
TXD19 25
RXD0 63 Receive Data Bus. These outputs carry 20-bit parallel data output from the transceiver to
RXD1 62 the protocol device, synchronized to RX_CLK. The data is valid on the rising edge of
RXD2 61 RX_CLK. These pins are high impedance during power-on reset.
RXD3 58
When the receiver is operating at 20 times REFCLK rate, the full width of the receive
RXD4 57
parallel bus is valid on the rising edge of RX_CLK. When the receiver is operating at 10
RXD5 56
times REFCLK rate, only the lower half of the receive parallel bus is valid on the rising
RXD6 55
edge of RX_CLK.
RXD7 54
When the on-chip encode/decode logic is bypassed, raw coded data is presented on the
RXD8 51
receive parallel bus. At full data rate, data is presented on bits RXD0 through RXD19. At
RXD9 50 Output (Hi-Z on
half data rate only bits RXD0 through RXD9 are valid
RXD10 49 power- up)
RXD11 47
When the on-chip encode/decode logic is utilized, bits RXD[0:7] make up the lower order
RXD12 46
data byte and bit RXD[16] becomes the K status bit for the lower order byte. Bits
RXD13 45
RXD[8:15] make up the higher order byte and bit RXD[17] becomes the K status bit for the
RXD14 44
higher order byte. Bits RXD[18] and RXD[19] are high impedance. At full data rate both
RXD15 43
lower and higher order bytes are de-serialized, decoded and output. At half data rate, only
RXD16 39
the lower order byte is de-serialized, decoded and output.
RXD17 38
The first received byte is always output on the lower order byte, and the first bit to be
RXD18 37
received is always presented in the lower order bit of a byte.
RXD19 36
Recovered Clock. Output clock that is synchronized to RXD[0:19]. RX_CLK is the
Output (low on
RX_CLK 52 recovered serial data rate clock divided by 10 or 20 depending on rate selection. RX_CLK
power-up)
is low during power-on reset.
Transmit Rate Select. When pulled high or left unconnected, the transmit path operates at
a data rate of 20 times REFCLK. This provides a data rate range of 2.0 to 2.6 Gbps. In this
mode, the width of the transmit parallel bus is 2 Bytes, either 20 bit coded data or 16 bit
TXRATE 77 Input (w/Pull-up) date plus two K-control bits for uncoded data. When pulled low, the transmit path operates
at a data rate of 10 times REFCLK. This provides a data rate range of 1.0 to 1.3 Gbps. In
this mode, the width of the transmit parallel bus is 1 Byte, either 10 bit coded data or 8 bit
date plus one K-control bit for uncoded data.
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