Datasheet
TLK2541
SLLS779B –JANUARY 2008–REVISED APRIL 2008
www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
R
t
= 50Ω, PREM = high, dc-coupled, See 750 913 1075
Figure 4
Preemphasis V
OD
, direct,
V
OD(p)
mV
V
OD(p)
= |VTXP – VTXN|
Rt = 50Ω, PREM = low, dc-coupled, See 700 850 1000
Figure 4
R
t
= 50Ω, PREM = high, dc-coupled, See 1500 1825 2150
Figure 4
Differential peak-to-peak output voltage
V
OD(pp_p)
mV
PP
with preemphasis
Rt = 50Ω, PREM = low, dc-coupled, See 1400 1700 2000
Figure 4
V
OD(d)
Deemphais output voltage, 500 600 800 mV
R
t
= 50Ω, dc-coupled, See Figure 4
|VTXP–VTXN|
V
OD(pp_d)
Differential, peak-to-peak output 1000 1300 1600 mV
PP
R
t
= 50Ω, dc-coupled, See Figure 4
voltage with deemphasis
V
(cmt)
Transmit common mode voltage range, 1000 1250 1400 mV
R
t
= 50Ω, See Figure 4
(VTXP + VTXN)/2
Receiver input voltage differential,
V
ID
200 1600 mV
|VRXP – VRXN|
Receiver common mode voltage range,
V
(cmr)
1000 1250 2250 mV
(VRXP + VRXN)/2
Ci Receiver input capacitance 2 pF
Differential output jitter at 2.5 Gbps, Random
*12 + deterministic, Based on K28.5/K28.5 .32
pattern
Serial data total jitter (peak-to-peak) UI
(1)
Differential output jitter at 1.25 Gbps,
0.19
Random*12 + deterministic, PRBS Pattern
Serial data total jitter (Random) Random Jitter (RMS) .016 UI
Differential output signal rise, fall time
t
t
, t
f
R
L
= 50Ω, C
L
= 5 pF, See Figure 4 150 ps
(20% to 80%)
Differential input jitter, random + .75
Jitter tolerance, Total jitter at serial
deterministic, PRBS pattern at zero crossing UI
input
at 1.25 Gbps
Jitter tolerance, Deterministic jitter at Differential input jitter, deterministic, PRBS .462
UI
serial input pattern at zero crossing at 1.25 Gbps
Differential input jitter, random + .60
Jitter tolerance, Total jitter at serial
deterministic, PRBS pattern at zero crossing UI
input
at 2.5 Gbps
Jitter tolerance, Deterministic jitter at Differential input jitter, deterministic, PRBS .37
UI
serial input pattern at zero crossing at 2.5 Gbps
t
d(Tx latency)
Tx latency with Coding Off See Figure 6 50 106
bits
Tx latency with Coding On 70 126
t
d(Rx latency)
Rx latency for Full Rate See Figure 9 81 100
bits
Rx latency for Half Rate 69 83
(1) UI is the time interval of one serialized bit.
Figure 4. Differential and Common-Mode Output Voltage Definitions
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