Datasheet

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SLLS574D − JULY 2003 − REVISED JULY 2007
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TERMINAL
DESCRIPTIONTYPE
NAME
DESCRIPTIONTYPE
NO.
RXD14 32
RXD15 31
RXD16 30
RXD17 29
RX_CLK 41 Output (low
on power up)
Recovered clock. Output clock that is synchronized to RXD. RX_CLK is the recovered serial data rate
clock divided by 20. RX_CLK is held low during power-on reset. These pins are also high impedance
when enable=0.
SYNC 25 Input
(w/pulldown)
Fast synchronization. When asserted high, the transmitter substitute the 18-bit pattern
111111111000000000 ,so that when the start/stop bits are framed around the data the receiver can
immediately detect the proper deserialization boundary. This is typically used during initialization of
the serial link.
PREEMPH 56 Input Preemphasis. When asserted, the serial transmit outputs have an extra output swing on the first bit
of any run-length of same value bits than when deasserted.
TEST PIN
ENABLE 24 Input
(w/pullup)
Device enable. When this pin is held low, the device is placed in power down mode. When asserted
high while the device is in power-down mode, the transceiver goes into power-on reset before
beginning normal operation.
LOOPEN 21 Input
(w/pulldown)
Loop enable. When LOOPEN is active high, the internal loop−back path is activated. The transmitted
serial data is directly routed internally to the inputs of the receiver. This provides a self-test capability
in conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
LOCKB 26 Output Receiver lock. When asserted low, it indicates that the receiver has acquired bit synchronization on
the data stream and has located the start/stop bits, so that the deserialized data presented on the
parallel receive bus is properly received. These pins are also high impedance when enable=0.
TESTEN 27 Input
(w/pulldown)
Test mode enable. This pin should be left unconnected or tied low.
POWER PIN
VDD 1, 9,
23, 38,
48
Supply Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
VDDA 55, 57 Supply Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and
transmitter.
GROUND PIN
GNDA 52, 58,
61
Ground Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX.
GND 5, 13,
18, 28,
33, 43
Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.