Datasheet

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     
SLLS574D − JULY 2003 − REVISED JULY 2007
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
LOOPEN
DINRXN
DINRXP
PREEMPH
Recovered
Clock
DOUTTXP
DOUTTXN
LOCKB
RX_CLK
TD(0−17)
RD(0−17)
Multiplying
Clock
Synthesizer
Interpolator and
Clock Recovery
ENABLE
18
TESTEN
20
Controls:
PLL,Bias,Rx,
Tx
18-Bit
Register
18-Bit
Register
GTX_CLK
Parallel to
Serial
MUX
MUX
Serial to
Parallel
20
18
Start/Stop
Decoder
Bit
Clock
Bit
Clock
Start/Stop
Encoder
transmit interface
The transmitter portion registers valid incoming 18-bit wide data (TXD[0:17]) on the rising edge of GTX_CLK.
The data is then framed with a start and a stop bit, serialized and transmitted sequentially over the differential
high-speed I/O channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times
creating a bit clock. This internal bit clock is fed to the parallel-to-serial shift register, which transmits data on
both the rising and falling edges of the bit clock providing a serial data rate that is 20 times the reference clock.
Data is transmitted LSB (D0) first.
transmit data bus
The transmit bus interface accepts 18-bit wide single-ended TTL parallel data at the TXD[0:17] pins. Data is
valid on the rising edge of GTX_CLK. The GTX_CLK is used as the word clock. The data and clock signals must
be properly aligned as shown in Figure 1. Detailed timing information can be found in the TTL input electrical
characteristics table.