Datasheet


    
SLLS427D − AUGUST 2000 − REVISED JULY 2003
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
transmitter/receiver characteristics
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
V
(ODp)
Vodp = |V
TXP
−V
TXN
|,
preemphasis V
OD
, direct
840 1050 1260 mV
V
OD(pp_P)
Differential, peak-to-peak output voltage
with preemphasis
R
t
= 50
Ω
, RREF = 200
Ω
, dc-coupled,
1680 2100 2520 mV
p-p
V
OD(d)
Vodd = |V
TXP
−V
TXN
|
,
deemphasis V
OD
, direct
R
t
= 50 Ω, RREF = 200 Ω, dc-coupled,
See Figure 12
760 950 1140 mV
V
OD(pp_d)
Differential, peak-to-peak output voltage
with deemphasis
1520 1900 2280 mV
p-p
V
(term)
Transmit termination voltage range
R
t
= 50 Ω, dc coupled, See Figure 15 V
DD
mV
V
(term)
Transmit termination voltage range
R
t
= 50 Ω, ac coupled, See Figure 16 1500 V
DD
−V
ID/2
mV
V
ID
Differential receiver input voltage
requirement, V
ID
=|V
RXP
− V
RXN
|
200 mV
V
(cmr)
Receiver common mode voltage range,
(V
RXP
+ V
RXN
)/2
1500 V
DD
−V
ID/2
mV
I
lkg(R)
Receiver input leakage current −10 10 µA
C
I
Receiver input capacitance 2 pF
Serial data total jitter (peak-to-peak)
Differential output jitter at 2.5 Gbps,
random + deterministic, PRBS pattern
0.15 UI
†
Serial data total jitter (peak-to-peak)
Differential output jitter at 1.5 Gbps,
random + deterministic, PRBS pattern
0.15 UI
†
t
r,
t
f
Differential output signal rise, fall time
(20% to 80%)
R
L
= 50 Ω, C
L
= 5 pF, See Figure 12 100 150 ps
Jitter tolerance
Differential input jitter, random +
determinisitc, PRBS pattern at zero
crossing
0.60 UI
†
t
d
(
Tx latency
) Tx latency See Figure 3 34 38 bits
t
d
(
Rx latency
) Rx latency See Figure 5 76 107 bits
†
UI is the time interval of one serialized bit.
V
(ODd)
V
(ODp)
V
(term)
V
(ODp)
V
(ODd)
Bit
Time
Bit
Time
t
r
t
f
V
OD(pp_d)
V
OD(pp_p)
Figure 12. Differential and Common-Mode Output Voltage Definitions