Datasheet

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TLK2201B
TLK2201BI
SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
RD0 – RD9 45, 44, 43, O Receive data. When in TBI mode (MODESEL = low) these outputs carry 10-bit parallel data output
41, 40, 39, from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and RBC1,
38, 36, 35, depending on the receive clock mode selected. RD0 is the first bit received.
34
When in the DDR mode (MODESEL = high) only RD0-RD4 are valid. RD5 – RD9 are held low. The
5-bit parallel data is clocked out of the transceiver on the rising edge of RBC0.
RBC0 31 O Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit
output data on RD0-RD9. The operation of these clocks is dependent upon the receive clock mode
RBC1 30
selected.
In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and
RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect.
The clocks are always expanded during data realignment and never slivered or truncated. RBC0
registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
In the normal rate mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is
aligned to the rising edge.
In the DDR mode, only RBC0 is valid and operates at 1/10 the serial data rate. Data is aligned to
both the rising and falling edges.
RBCMODE 32 I Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output
on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is
P/D
(1)
output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full
baud-rate clock is output on RBC0 and RBC1 is held low.
SYNCENlow. 24 I Synchronous function enable. When SYNCEN is high, the internal synchronization function is
SYNCENlow. P/U
(2)
activated. When this function is activated, the transceiver detects the K28.5 comma character
SYNCENlow (0011111 negative beginning disparity) in the serial data stream and realigns data on byte
boundaries if required. When SYNCEN is low, serial input data is unframed in RD0 – RD9.
SYNC/PASS 47 O Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in
the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In
PRBS test mode (PRBSEN=high), SYNC/PASS outputs the status of the PRBS test results
(high=pass).
LOS 26 O Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.
If magnitude of RXP – RXN > 150 mV, LOS = 1, valid input signal
If magnitude of RXP – RXN < 150 mV and >50 mV, LOS is undefined
If magnitude of RXP – RXN < 50 mV, LOS = 0, loss of signal
MODESEL 15 I Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface.
P/D
(1)
When low the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected.
The default mode is the TBI.
TEST
LOOPEN 19 I Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The TXP and TXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational
state with external serial outputs and inputs active.
TCK 49 I Test clock. IEEE1149.1 (JTAG)
JTDI 48 I Test data input. IEEE1149.1 (JTAG)
JTDO 27 O Test data output. IEEE1149.1 (JTAG)
JTRSTN 56 I Reset signal. IEEE1149.1 (JTAG)
P/U
(2)
JTMS 55 I Test mode select. IEEE1149.1 (JTAG)
P/U
(2)
ENABLE 28 I When this terminal is low, the device is disabled for Iddq testing. RD0 - RD9, RBCn, TXP, and
P/U
(2)
TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When
ENABLE is high, the device operates normally.
PRBSEN 16 I PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS
P/D
(1)
verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive
inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.
(1) P/D = Internal pulldown
(2) P/U = Internal pullup
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