Datasheet

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t
r
t
f
CLOCK
80%
50%
20%
t
r
t
f
2V
0.8V
DATA
1.4V
LVTTL OUTPUT SWITCHING CHARACTERISTICS
TRANSMITTER TIMING REQUIREMENTS
TLK2201B
TLK2201BI
SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008
Figure 9. TTL Data I/O Valid Levels for AC Measurement
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
r(RBC)
Clock rise time 80% to 20% output voltage, C = 5 pF (see Figure 9 ) 0.3 1.5
ns
t
f(RBC)
Clock fall time 0.3 1.5
t
r
Data rise timer 0.3 1.5
ns
t
f
Data fall time 0.3 1.5
Data setup time (RD0..RD9),
t
su(D1)
TBI normal mode (see Figure 3 ) 2.5 ns
Data valid prior to RBC0 rising)
Data hold time (RD0..RD9),
t
h(D1)
TBI normal mode (see Figure 3 ) 2 ns
Data valid after RBC0 rising
t
su(D2)
Data setup time (RD0..RD4) DDR mode, R
ω
= 125 MHz (see Figure 4 ) 2 ns
t
h(D2)
Data hold time (RD0..RD4) DDR mode, R
ω
= 125 MHz (see Figure 4 ) 0.8 ns
t
su(D3)
Data setup time (RD0..RD9) TBI half-rate mode, R
ω
= 125 MHz (see Figure 2 ) 2.5 ns
t
h(D3)
Data hold time (RD0..RD9) TBI half-rate mode, R
ω
= 125 MHz (see Figure 2 ) 1.5 ns
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
su(D4)
Data setup time (TD0..TD9) 1.6
TBI modes ns
t
h(D4)
Data hold time (TD0..TD9) 0.59
(1)
t
su(D5)
Data setup time (TD0..TD9) 0.7
DDR modes ns
t
h(D5)
Data hold time (TD0..TD9) 0.5
t
r
, t
f
TD[0,9] Data rise and fall time See Figure 9 2 ns
(1) Measured at 1.25V (midpoint of V
IL
and V
IH
) with input switching between 0V and V
DD
.
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