Datasheet

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TRANSMITTER/RECEIVER CHARACTERISTICS
C
L
5pF
C
L
5pF
50 Ω
50 Ω
80%
50%
20%
t
r
t
r
t
f
t
f
80%
50%
20%
∼ V
∼ V
∼ V
∼ V
80%
20%
0 V
∼ 1V
∼ −1V
TX+
TX−
VOD
TLK2201B
TLK2201BI
SLLS585C – NOVEMBER 2003 – REVISED FEBRUARY 2008
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Rt = 50 Ω 600 850 1100
Vod = |TxD – TxN| mV
Rt = 75 Ω 800 1050 1200
Rt = 50 Ω 1000 1250 1400
V
(cm)
Transmit common mode voltage range mV
Rt = 75 Ω 1000 1250 1400
Receiver Input voltage requirement,
200 1600 mV
Vid = |RxP - RxN|
Receiver common mode voltage range,
1000 1250 2250 mV
(RxP + RxN)/2
I
lkg(R)
Receiver input leakage current – 350 350 µ A
C
I
Receiver input capacitance 2 pF
Differential output jitter, Random +
t
(TJ)
Serial data total jitter (peak-to-peak) deterministic, PRBS pattern, 0.24 UI
R
ω
= 125 MHz
Differential output jitter, PRBS pattern,
t
(DJ)
Serial data deterministic jitter (peak-to-peak) 0.12 UI
R
ω
= 125 MHz
R
L
= 50 Ω , C
L
= 5 pF,
t
r
, t
f
Differential signal rise, fall time (20% to 80%) 100 250 ps
See Figure 7 and Figure 8
Differential input jitter, Random +
Serial data jitter tolerance minimum required
deterministic, 0.25 UI
eye opening, (per IEEE-802.3 specification)
R
ω
= 125 MHz
Receiver data acquisition lock time from 500 µ s
powerup
Bit
Data relock time from loss of synchronization 1024
times
TBI modes See Figure 1 19 20
t
d(Tx latency)
Tx latency UI
DDR 29 30
mode
TBI modes See Figure 6 21 31
t
d(Rx latency)
Rx latency UI
DDR 27 34
mode
Figure 7. Differential and Common-Mode Output Voltage Figure 8. Transmitter Test Setup
Definitions
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