Datasheet

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SLLS591C− OCTOBER 2003 − REVISED JULY 2007
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
loop-back testing
The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling
this pin causes serial transmitted data to be routed internally to the receiver. The parallel data output can be
compared to the parallel input data for functional verification. (The external differential output is held in a
high-impedance state during the loop-back testing.)
power-on reset
Upon application of minimum valid power, the TLK1521 generates a power-on reset. During the power-on reset,
the RXD pins are tri-stated and RX_CLK is held low. The length of the power-on reset cycle is dependent upon
the REFCLK frequency, but is less than 1 ms in duration.
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
SIGNAL PIN
DOUTTXP 60
Output
(High-Z
Serial transmit outputs. DOUTTXP and DOUTTXN are differential serial outputs that interface to coppe
r
or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK value
.
DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are active when
DOUTTXN 59
(High-Z
power up)
or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK value.
DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are active when
LOOPEN is low. During power-on reset, these pins are high impedance.
DINRXP 54
Input
Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a
copper or an optical I/F module.
DINRXN 53
Input
Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a
copper or an optical I/F module.
GTX_CLK 8 Input Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter
interface TXD. The frequency range of GTX_CLK is 25 MHz to 65 MHz. The transmitter uses the rising
edge of this clock to register the 18-bit input data (TXD) for serialization.
TXD0 62
TXD1 63
TXD2 64
TXD3 2
TXD4 3
TXD5 4
TXD6 6
TXD7 7
Transmit data bus. These inputs carry the 18-bit parallel data output from a protocol device to the
TXD8 10
Input
Transmit data bus. These inputs carry the 18-bit parallel data output from a protocol device to the
transceiver for encoding, serialization and transmission. This 18-bit parallel data is clocked into the
TXD9 11
Input
transceiver for encoding, serialization and transmission. This 18-bit parallel data is clocked into the
transceiver on the rising edge of GTX_CLK as shown in Figure 6.
TXD1 12
transceiver on the rising edge of GTX_CLK as shown in Figure 6.
TXD11 14
TXD12 15
TXD13 16
TXD14 17
TXD15 19
TXD16 20
TXD17 22