Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers, deserialisers VML HTQFP 64

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SLLS591C− OCTOBER 2003 − REVISED JULY 2007

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Hot Plug Protection

D 0.5 to 1.3 Gigabits Per Second (Gbps)

Serializer/Deserializer

D High-Performance 64-Pin HTQFP Thermally

Enhanced Package (PowerPAD)

D 2.5-V Power Supply for Low Power

Operation

D Selectable Signal Preemphasis for Serial

Output

D Interfaces to Backplane, Copper Cables, or

Optical Converters

D Lock Indication and Sync Mode for Fast

Initialization

D 18-Bit Parallel Busses for Flexible Interface

Applications

D On-chip PLL Provides Clock Synthesis

From Low-Speed Reference

D Receiver Differential Input Thresholds

200 mV Min

D Rated for Industrial Temperature Range

D Typical Power: 288 mW at 1.3 Gbps

D Ideal for High-Speed Backplane

Interconnect and Point-to-Point Data Link

D Passive Receive Equalizer

RXD3

RXD4

RXD5

RXD6

GND

RXD7

RX_CLK

RXD8

RXD9

RXD10

RXD11

RXD12

RXD13

GND

TXD3

TXD4

TXD5

GND

TXD6

TXD7

GTX_CLK

TXD8

TXD9

TXD10

GND

TXD11

TXD12

TXD13

RXD1

DINRXP

63 62 61 60 5964 58

TXD0

GNDA

DOUTTXP

DOUTTXN

GNDA

PREEMPH

LOCKB

TESTEN

GND

RXD17

TXD15

TXD16

LOOPEN

TXD17

ENABLE

SYNC

56 55 5457 53 52

TXD14

DINRXN

GNDA

51 50 49

RXD16

RXD15

RXD14

RXD0

RXD2

TXD2

TXD1

GND

DDA

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

Summary of content (23 pages)

PAGE 1
Serializer/Deserializer D High-Performance 64-Pin HTQFP Thermally D D D D 18-Bit Parallel Busses for Flexible Interface D D D D D D Applications On-chip PLL Provides Clock Synthesis From Low-Speed Reference Receiver Differential Input Thresholds 200 mV Min Rated for Industrial Temperature Range Typical Power: 288 mW at 1.
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SLLS591C− OCTOBER 2003 − REVISED JULY 2007 description The TLK1521 is a member of the WizardLink family of multi-gigabit transceivers, intended for use in high-speed bidirectional point-to-point data transmission systems. The TLK1521 supports an effective serial interface speed of 500 Mbps to 1.3 Gbps, providing up to 1.17 Gbps of data bandwidth.
PAGE 3
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 functional block diagram TD(0−17) 18-Bit Register LOOPEN DOUTTXP 18 Start/Stop Encoder Parallel to Serial 20 DOUTTXN Bit Clock PREEMPH Multiplying Clock Synthesizer GTX_CLK TESTEN Controls: PLL,Bias,Rx, Tx ENABLE Bit Clock Interpolator and Clock Recovery MUX Recovered Clock LOCKB RD(0−17) 18-Bit Register RX_CLK 18 Start/Stop Decoder 20 Serial to Parallel MUX DINRXP DINRXN transmit interface The transmitt
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SLLS591C− OCTOBER 2003 − REVISED JULY 2007 GTX_CLK TXDn tsu th Figure 1. Transmit Timing Waveform transmission latency The data transmission latency of the TLK1521 is defined as the delay from the initial 18-bit word load to the serial transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly.
PAGE 5
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 parallel-to-serial The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the framing logic and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the internally generated bit clock, which is 10 times the GTX_CLK input frequency. The LSB (TD0) is transmitted first as shown in Figure 3.
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SLLS591C− OCTOBER 2003 − REVISED JULY 2007 data reception latency The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with RXD0 received as first bit. The receive latency is fixed once the link is established. However, due to silicon process variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly.
PAGE 7
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 random lock synchronization (continued) The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive multitransition (RMT). This occurs when more than one low-high transition takes place per clock cycle over multiple clock cycles.
PAGE 8
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 loop-back testing The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling this pin causes serial transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. (The external differential output is held in a high-impedance state during the loop-back testing.
PAGE 9
TERMINAL NAME NO. RXD0 51 RXD1 50 RXD2 49 RXD3 47 RXD4 46 RXD5 45 RXD6 44 RXD7 42 RXD8 40 RXD9 39 RXD10 37 RXD11 36 RXD12 35 RXD13 34 RXD14 32 RXD15 31 RXD16 30 RXD17 29 RX_CLK TYPE SLLS591C− OCTOBER 2003 − REVISED JULY 2007 DESCRIPTION Output (High-Z on power up) Receive data bus. These outputs carry 18-bit parallel data output from the transceiver to the protocol device, synchronized to RX_CLK.
PAGE 10
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 TERMINAL NAME NO. TYPE DESCRIPTION GROUND PIN GNDA GND 52, 58, 61 Ground Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX. 5, 13, 18, 28, 33, 43 Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers. absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (see Note 1) . . . . . . . .
PAGE 11
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 DISSIPATION RATING TABLE PACKAGE PAP64‡ PAP64§ TA ≤ 25°C POWER RATING DERATING FACTOR† ABOVE TA = 25°C TA = 70°C POWER RATING 3.22 W 32.15 mW/°C 1.77 W 0.94 W 9.46 mW/°C 0.52 W PAP64¶ 0.68 W 6.
PAGE 12
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 TTL input electrical characteristics over recommended operating conditions (unless otherwise noted) TTL Signals: TXD0 ...TXD17, GTX_CLK, LOOPEN, SYNC, PREEMPH PARAMETER TEST CONDITIONS MIN TYP 2 MAX UNIT VIH VIL High-level input voltage See Figure 6 Low-level input voltage See Figure 6 3.6 V 0.8 V IIH IIL High-level input current Low-level input current VDD = MAX, VIN = 2 V VDD = MAX, VIN = 0.
PAGE 13
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 TTL output switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 2.1 2.3 GND 0.25 MAX UNIT VOH VOL High-level output voltage Low-level output voltage IOH= −1 mA, VDD = MIN IOL= 1 mA, VDD = MIN tr(slew) tf(slew) Magnitude of RX_CLK, RXD slew rate (rising) 0.8 V to 2 V, C = 5 pF, See Figure 10 0.
PAGE 14
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 transmitter/receiver characteristics PARAMETER TEST CONDITION MIN TYP MAX UNIT VOD(p) VOD(p) = |VTXP-VTXN|, Preemphasis VOD DC-coupled. Preemphasis = high, See Figure 8 730 945 1280 mV VOD(pp−p) Differential, peakĆto-peak output voltage with preemphasis DC-coupled. Preemphasis = high, See Figure 8 1460 1890 2560 mV VOD(d) VD(d) = |VTXP-VTXN|, De-emphasis VOD DC-coupled.
PAGE 15
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 80% 50% 20% DOUTXP tr tf 80% 50% 20% DOUTXN tf tr +V DOUTXP DOUTXN 80% 0V 20% −V tr tf Figure 9.
PAGE 16
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 Recommended use of 0.01-µF capacitor per VDD terminal 0.
PAGE 17
TXP SLLS591C− OCTOBER 2003 − REVISED JULY 2007 RXP VDD ZO ZO 5 kΩ ZO 7.5 kΩ ZO TXN Transmitter + _ GND RXN Media Receiver Figure 11. High-Speed I/O Directly Coupled Mode TXP RXP VDD ZO ZO 5 kΩ ZO 7.5 kΩ ZO TXN Transmitter + _ GND RXN Media Receiver Figure 12. High-Speed I/O AC-Coupled Mode AC-coupling is only recommended if the parallel TX data stream is encoded to achieve a dc-balanced data stream.
PAGE 18
SLLS591C− OCTOBER 2003 − REVISED JULY 2007 Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package application report, TI (SLMA002), available via the TI Web pages beginning at URL: http://www.ti.com. Figure 13. Example of a Thermal Land For the TLK1521, this thermal land should be grounded to the low-impedance ground plane of the device.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.