Datasheet


    
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
DINRXN
DINRXP
53
54
I Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a
copper or an optical I/F module.
DOUTTXN
DOUTTXP
59
60
O Serial transmit outputs (Hi-Z on power up). DOUTTXP and DOUTTXN are differential serial outputs that
interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the
GTX_CLK value. DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high
and are active when LOOPEN is low. During power-on reset these terminals are high impedance.
ENABLE 24 I Device enable (w/pullup). When this terminal is held low, the device is placed in power-down mode. Only
the signal detect circuit on the serial receive pair is active. When asserted high while the device is in
power-down mode, the transceiver goes into power-on reset before beginning normal operation.
GND 5, 13,
18, 28,
33, 43
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
GNDA 52, 58,
61
Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX.
GTX_CLK 8 I Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter
interface signals TX_EN, TX_ER and TXD. The frequency range of GTX_CLK is 30 MHz to 75 MHz.
The transmitter uses the rising edge of this clock to register the 16-bit input data (TXD) for serialization.
LCKREFN 25 I Lock to reference (w/pullup). When LCKREFN is low, the receiver clock is frequency locked to
GTX_CLK. This places the device in a transmit only mode since the receiver is not tracking the data.
When LCKREFN is asserted low, the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER,
RX_DV/LOS are in a high-impedance state.
When LCKREFN is deasserted high, the receiver is locked to the received data stream and must receive
valid codes from the synchronization state machine before the transmitter is enabled.
LOOPEN 21 I Loop enable (w/pulldown). When LOOPEN is active high, the internal loop-back path is activated. The
transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational state
with external serial outputs and inputs active.
PRBSEN 26 I PRBS test enable (w/pulldown). When asserted high results of pseudorandom bit stream (PRBS) tests
can be monitored on the RX_ER/PRBS_PASS terminal. A high on PRBS_PASS indicates that valid
PRBS is being received.
RREF 56 I Reference resistor. The RREF terminal is used to connect to an external reference resistor. The other
side of the resistor is connected to analog V
DD
. The resistor is used to provide an accurate current
reference to the transmitter circuitry.
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD8
RXD9
RXD10
RXD11
RXD12
RXD13
RXD14
RXD15
51
50
49
47
46
45
44
42
40
39
37
36
35
34
32
31
O Receive data bus (Hi-Z on power up). These outputs carry 16-bit parallel data output from the transceiver
to the protocol device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as
shown in Figure 13. These terminals are in high-impedance state during power-on reset.