Datasheet


    
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
block diagram
LOOPEN
DINRXN
DINRXP
BIAS
RREF
PRBSEN
Recovered
Clock
DOUTTXP
DOUTTXN
RX_CLK
RX_DV/LOS
RX_ER
PRBS_PASS
TX_EN
TD(0−15)
8
8
RD(0−15)
PRBS
Verification
Multiplying
Clock
Synthesizer
Interpolator and
Clock Recovery
ENABLE
10
PRBSEN
PRBSEN
TX_ER
PRBSEN
TESTEN
10
10
Controls:
PLL,Bias,Rx,
Tx
8B/10B
Encoder
16 Bit
Register
8B/10B
Encoder
16 Bit
Register
PRBS
Generator
MUX
GTX_CLK
2:1
MUX
Parallel to
Serial
10
2:1
MUX
2:1
MUX
Serial to
Parallel
10
1:2
MUX
10
10
8
8
2:1
MUX
Data
Comma
Detect
and 8B/10B
Decoding
10
Bit
Clock
Bit
Clock
Comma
Detect
and 8B/10B
Decoding
Signal Detect
(LOS)
Figure 1. TLK1501 Block Diagram