Datasheet

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SLLS428F − JUNE 2000 − REVISED JANUARY 2004
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
transmitter/receiver characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OD(p)
Preemphasis V
OD
, direct,
V
OD(p) =
|VTXP − VTXN|
840 1050 1260 mV
V
OD(pp_p)
Differential, peak-to-peak output voltage with
preemphasis
Rt = 50
Ω
, RREF = 200
Ω
, dc-coupled,
1680 2100 2520 mV
p-p
V
OD(d)
Deemphais output voltage,
|VTXP − VTXN|
Rt = 50 Ω, RREF = 200 Ω, dc-coupled,
See Figure 12
760 950 1140 mV
V
OD(pp_d)
Differential, peak-to-peak output voltage with
de-emphasis
1520 1900 2280 mV
p-p
V
(term)
Transmit termination voltage range,
Rt = 50 Ω, dc-coupled, See Figure 15 V
DD
mV
V
(term)
Transmit termination voltage range,
Rt = 50 Ω, ac-coupled, See Figure 15
1500
V
DD −
V
ID/2
mV
V
ID
Receiver input voltage differential,
|VRXP – VRXN|
200 mV
V
(cmr)
Receiver common mode voltage range,
(VRXP + VRXN)/2
1500 V
DD −
V
ID/2
mV
I
lkg
Receiver input leakage current −10 10 µA
C
i
Receiver input capacitance 2 pF
Serial data total jitter (peak-to-peak)
Differential output jitter at 1.5 Gbps,
Random + deterministic, PRBS pattern
0.10 UI
†
Serial data total jitter (peak-to-peak)
Differential output jitter at 0.6 Gbps,
Random + deterministic, PRBS pattern
0.10 UI
†
t
t,
t
f
Differential output signal rise, fall time
(20% to 80%)
R
L
= 50 Ω, C
L
= 5 pF, See Figure 12 100 150 ps
Jitter tolerance
Differential input jitter, random +
determinisitc, PRBS pattern at zero
crossing
0.60 UI
t
d
(
Tx latency)
Tx latency
See Figure 2 34 38
bits
t
d
(
Tx latency)
Tx latency
GTX_CLK = 62.4 MHz 35 37
bits
t
d
(
Rx latency)
Rx latency
See Figure 5 76 107
bits
t
d
(
Rx latency)
Rx latency
GTX_CLK = 62.4 MHz 81 96
bits
†
UI is the time interval of one serialized bit.
V
OD(d)
V
OD(p)
V
(term)
V
OD(p)
V
OD(d)
Bit
Time
Bit
Time
t
r
t
f
V
OD(pp_p)
V
OD(pp_d)
Figure 12. Differential and Common-Mode Output Voltage Definitions