Datasheet

Typical Test and Setup Configurations
2-6
Figure 2–4. TLK1501 Serial PRBS BERT Test Configuration
TX_EN
GTX_CLK
TX_EN
TX_ER
TX+
RX–
RX+
TX–
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
TLK1501EVM #1
Evaluation Board EVM1
PRBS Disabled
RD 0-15
EVM #1
TX Data Out 0-17
Parallel BERT
Frequency = 30-80 MHz
CLK IN
RX Data In 0-17
18 bits
Receiver BERT
Transmitter BERT
CLK Out
18 bits
TD 0-15
GTX_CLK
RX–
RD 0-15
TD 0-15
RX_CLK
RX_ER
Rx_DV
TLK1501EVM #2
Evaluation Board EVM2
PRBS Disabled
TX–
RX+
TX+
Synchronous
Asynchronous
Board configued to
send IDLE pattern:
TX_EN = 0
TX_ER = 0
Jumper Selection
TX_EN
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
EVM #2
EXT INPUT
HP8133A
Pulse Generator
Channel 1
O/P
Trigger
16 bits
2 bits
Channel
1
(Asynchronous to BERT)