Datasheet

Typical Test and Setup Configurations
2-4
If a parallel BERT is not available, the designer can take advantage of the
built-in test mode of the device, see Figure 2–2. If the designer asserts the
PRBSEN pin high this results in a pseudorandom bit pattern to be transmitted.
This pin also puts the receiver in a mode to detect a valid PRBS pattern. A valid
pattern is indicated by the PRBSPASS pin indicating high. This test only
validates the high-speed serial portion of the device and system interconnects.
The PRBS pattern is compatible with most serial BERT test equipment. This
function allows the operator to isolate and test the transmitter and receiver
independently. A typical configuration is shown in Figure 2–3. The dashed
lines represent optional connections that can be made monitoring eye patterns
and measuring jitter.
Figure 2–2. TLK1501 Serial Loop-Back Test Configuration
Channel 1
TDS820 Digital
Oscilloscope
TX_EN
GTX_CLK
PRBS
2^7-1
TX–
RX–
RX+
TX+
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
TLK1501EVM
Evaluation Board
RD 0-15
PRBS_PASS
PRBS 2^7-1
CH1
HP83480 or
Tek 11801
Trigger
CH2
Digital
Oscilloscope
EXT
INPUT
HP8133A
Pulse Generator
Channel 1
O/P
TRIGGER
OUT
Jumper Selection