Datasheet

Typical Test and Setup Configurations
2-3
TLK1501 EVM Board Configuration
2.1 Typical Test and Setup Configurations
The following configurations are used to evaluate and test the TLK1501
transceiver. The first configuration is a serial loopback of the high-speed
signals shown in Figure 2–1. The serial loopback allows the designer to
evaluate most of the functions of both transmitter and receiver sections of the
TLK1501 device. To test a system, a parallel bit error rate tester (BERT)
generates a predefined parallel bit pattern. The pattern is connected to the
transmitter through parallel connectors TD0–TD15. Additionally, two control
pins TX_ER and TX_EN are configured by the BERT for valid data
transmission (TX_ER low and TX_EN high). The TLK1501 device encodes,
serializes, and presents the data on the high-speed serial pair. The serial TX
data is then looped back to the receiver side and the device deserializes,
decodes, and presents the data on the receive side RD0–RD15. The data and
indication bits (RX_DV and RX_ER) are received by the BERT and compared
against the transmitted pattern and monitored for valid data and errors. If any
bit errors are received, a bit error rate is evaluated at the parallel receive BERT.
Figure 2–1. TLK1501 Serial Loop-Back Test Configuration
TX_EN
TX Data Out 0-17
18 bits
Parallel BERT
Frequency = 30-80 MHz
CLK IN
RX Data In 0-17
18 bits
Receiver BERT
GTX_CLK
TD 0-15
TX_EN
TX_ER
RD 0-15
RX_ER
RX_DV
RX CLK
TX+
RX–
RX+
TX–
(Asynchronous to BERT)
EXT INPUT
HP8133A
Pulse Generator
Channel 1
O/P
GND
LOOPEN
TX_ER
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
J7
TLK1501EVM
Evaluation Board
Jumper Selection
CLK OUT