Datasheet

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JMP7
PRBSEN
SYNCEN
ENABLE
RBCMODE
LOOPEN
GND
TLK1221
8
9
GND
RD[9:0]
TD[9:0]
GND
TD[9:0]
VDD
237 6 5 4
89 237 6 5 4
JMP6
01
01
REFCLK
R
X
N
RXPTXP
TX
N
JMP8
RBC0
RBC1
SYNC
GND
JMP9
VDDPLL
VDD
JMP10
VDDA
VDD
VDD
GND
GND
VDDPLL
VDDA
RD[9:0]
ANALYZER
ANALYZER
CLOCK
CLOCK
GENERATOR
PARALLEL ANALYZER
POWER
SUPPLY
2.5V
+ -
Typical Test and Setup Configurations
Figure 5. TLK1221 EVM Serial PRBS 2^7-1 Self-Test Configuration
If a parallel BERT is not available, the system designer can take advantage of the built-in-test mode of the
device, see Figure 6 . If the designer asserts the PRBSEN pin high, a Pseudo Random Bit Pattern will be
transmitted. This pin also puts the receiver in a mode to detect a valid PRBS pattern. A valid pattern is
indicated by the SYNC pin indicating high. This test only validates the high-speed serial portion of the
device and the system interconnects. The PRBS pattern is compatible with most serial BERT test
equipment. This function allows the operator to isolate and test the transmitter and receiver independently.
A typical configuration is shown in Figure 6 . The dashed lines represent optional connections that can be
made for monitoring eye patterns and measuring jitter.
6 TLK1221 Ethernet Transceiver Evaluation Module (EVM) SLLU100 – September 2007
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