Datasheet

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JMP7
PRBSEN
SYNCEN
ENABLE
RBCMODE
LOOPEN
GND
TLK1221
8
9
GND
RD[9:0]
TD[9:0]
GND
TD[9:0]
VDD
237 6 5 4
89 237 6 5 4
JMP6
01
01
REFCLK
RX
N
RXPTXP
TX
N
JMP8
RBC0
RBC1
SYNC
GND
JMP9
VDDPLL
VDD
JMP10
VDDA
VDD
VDD
GND
GND
VDDPLL
VDDA
RD[9:0]
ANALYZER
TD[9:0]
GENERATOR
ANALYZER
CLOCK
CLOCK
GENERATOR
PARALLEL BERT
POWER
SUPPLY
2.5V
+ -
Typical Test and Setup Configurations
(TD0-TD4 for DDR mode). The TLK1221 device serializes and presents the data on the high-speed serial
pair (TXP/TXN). The serial TX data is then looped back to the receiver side and the device de-serializes
and presents the data on the receiver side RD0–RD9 (RD0-RD4 for DDR mode). The data is received by
the BERT and compared against the transmitted pattern and monitored for valid data and errors. If any bit
errors are received, a bit-error rate is evaluated at the parallel-receive BERT.
Figure 4. TLK1221 EVM External Serial Loopback Test Configuration
If a parallel data generator is not available, placing jumpers on the additional TD pins of the header block
JMP6 will allow a static pattern to be received by the parallel TD bus, serialized, looped back into the
serial receiver, and de-serialized where it can be viewed with an analyzer. However, unless the pattern
jumpered onto the TD pins includes the comma pattern and the SYNCEN pin is high, the data will be
unframed data and the values of the RD[9:0] pins may not be aligned with the corresponding TD[9:0] pins.
SLLU100 – September 2007 TLK1221 Ethernet Transceiver Evaluation Module (EVM) 5
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