Datasheet

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89
GND
RD [9 :0]
TD [9 :0]
GND
TD [9 :0]
VDD
23
7
6
5
4
89
2
3
7
6 5
4
01
0
1
PARALLEL
LOOPBACK
STATICCLOCK
ONTD[9:0]
JMP6
4 Typical Test and Setup Configurations
Typical Test and Setup Configurations
next to the RD and TD pins provide a convenient ground reference for a scope probe or coax cables. The
additional TD row and VDD pins allow a static pattern to be driven into the TD bus by placing jumpers
across either the TD and VDD pins for a HIGH, or TD and GND pins for a LOW eliminating the need for
cables for quick tests. The extra row of TD can also be used to monitor the signals on the TD pins while
simultaneously looping back into the RD pins. Figure 3 shows a clock pattern (0101010101) on TD[9:0]
being looped back onto the RD[9:0] pins.
Figure 3. Parallel Loop Back with Static Data Pattern
Table 1. Default Transceiver – Board Configuration as Shipped
Designator Function Condition
JMP9 VDD and VDDPLL Bridge Joins the VDD and VDDPLL power planes
JMP10 VDD and VDDA Bridge Joins the VDD and VDDA power planes
JMP7 PRBSEN Jumper installed (logic 0) – disables the TLK1221 PRBS internal production test mode
JMP7 SYNCEN Jumper installed (logic 0) – disables the TLK1221 comma-detection circuitry
JMP7 ENABLE Jumper not installed (logic 1) – this pulls up the enable pin for normal operation
JMP7 RBCMODE Jumper not installed (logic 1) – for a 1/10 baud-rate clock on RBC0 (a non-DDR mode)
JMP7 LOOPEN Jumper installed (logic 0) – disables the TLK1221 internal loopback mode
C1, C3 TX AC-Coupling Capacitors These capacitors (normally installed) are provided to ac-couple the transmitted serial
signal.
C2, C4 RX AC-Coupling These capacitors (normally installed) are provided to ac-couple the received serial
Capacitors signal.
Table 2. Configuration Changes Necessary for DC-Coupling of the High-Speed Signals
Designator Function Condition
C1, C3 TX AC-Coupling Capacitors Remove capacitors and install 0- Ω resistors
C2, C4 RX AC-Coupling
Capacitors
This section presents the typical test and setup configuration used to evaluate and test the transceiver.
The printed-circuit board construction and characteristics are included in chapter 5.
The following configurations are used to evaluate and test the TLK1221 transceiver. The first configuration
is an external serial loopback of the high-speed signals shown in Figure 4 . The serial loopback allows the
system designer to evaluate most of the functions of the transmitter and receiver sections of the TLK1221
device. To test a system, a parallel Bit Error Rate Tester (BERT) generates a predefined DC-balanced
parallel bit pattern. The pattern is connected to the transmitter through parallel connectors TD0-TD9
4 TLK1221 Ethernet Transceiver Evaluation Module (EVM) SLLU100 – September 2007
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