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5.3 Board Layouts
+
+
+
LOOPEN
RBCMODE
ENABLE
SYNCEN
PRBSEN
└
PULL -UPS
GND
GNDGND
VDD
TD
GND
TD
RD
GND
0
1
3
2
6
5
4
9
8
7
9
8
7
6
5
4
3
2
1
0
VDD
TD
GND
TD
RD
GND
RBC0
RBC1
SYNC
GND
VDDA
VDDPLL VDD
VDD
VDD_LED
VDDPLL_LED
REV.
TLK1221 EVM
VDDA
6492635
REFCLK
RX
N
RXP
TXP
TX
N
VDDA_LED
GND VDD
GND
VDDPLL
PIN 1
Schematic, Bill of Materials, and Board Layouts
Figure 9. TLK1221 Board Layout: Top (Layer 1)
SLLU100 – September 2007 TLK1221 Ethernet Transceiver Evaluation Module (EVM) 11
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