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User's Guide

SLLU100 – September 2007

TLK1221 Ethernet Transceiver Evaluation Module (EVM)

The Texas Instruments TLK1221 SERDES Evaluation Module (EVM) board is used to evaluate the

TLK1221 device (40-pin 6-mm × 6-mm QFN PowerPAD™) for point-to-point data transmission

applications. The board enables the system designer to connect 50- Ω parallel buses to both transmitter

and receiver connectors. Using high-speed PLL technology, the TLK1221 serializes and transmits data

along one differential pair. The receiver portion of the device de-serializes and presents data on the

parallel bus. The high-speed (up to 1.3 Gbps) data lines interface to four 50- Ω controlled-impedance SMA

connectors.

Contents

1 Introduction ................................................................................................................... 2

2 TLK1221 EVM Kit Contents ................................................................................................ 2

3 TLK1221 EVM Board Configuration ....................................................................................... 2

4 Typical Test and Setup Configurations ................................................................................... 4

5 Schematic, Bill of Materials, and Board Layouts ........................................................................ 9

List of Figures

1 Parallel Signal Header Block ............................................................................................... 3

2 Parallel Signal Header Block ............................................................................................... 3

3 Parallel Loop Back with Static Data Pattern ............................................................................. 4

4 TLK1221 EVM External Serial Loopback Test Configuration .......................................................... 5

5 TLK1221 EVM Serial PRBS 2^7-1 Self-Test Configuration ............................................................ 6

6 TLK1221 EVM Serial PRBS 2^7-1 Self-Test Configuration ............................................................ 7

7 TLK1221 EVM Serial PRBS 2^7-1 Test Configuration ................................................................. 8

8 TLK1221 EVM Schematic .................................................................................................. 9

9 TLK1221 Board Layout: Top (Layer 1) .................................................................................. 11

10 TLK1221 Board Layout: GND (Layer 2) ................................................................................. 12

11 TLK1221 EVM Board Layout: Internal Signal (Layer 3) ............................................................... 13

12 TLK1221 Board Layout: GND (Layers 4,6,8,9) ......................................................................... 14

13 TLK1221 Board Layout: Internal Signal and VDDPLL (Layer 5) ..................................................... 15

14 TLK1221 Board Layout: VDDA and VDD (Layer 7) ................................................................... 16

15 TLK1221 Board Layout: Bottom (Layer 10) ............................................................................. 17

List of Tables

1 Default Transceiver – Board Configuration as Shipped ................................................................ 4

2 Configuration Changes Necessary for DC-Coupling of the High-Speed Signals.................................... 4

3 TLK1221 EVM Bill of Materials ........................................................................................... 10

4 TLK1221 EVM PCB Layer Construction ................................................................................ 18

SLLU100 – September 2007 TLK1221 Ethernet Transceiver Evaluation Module (EVM) 1

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Summary of content (21 pages)

PAGE 1
User's Guide SLLU100 – September 2007 TLK1221 Ethernet Transceiver Evaluation Module (EVM) The Texas Instruments TLK1221 SERDES Evaluation Module (EVM) board is used to evaluate the TLK1221 device (40-pin 6-mm × 6-mm QFN PowerPAD™) for point-to-point data transmission applications. The board enables the system designer to connect 50-Ω parallel buses to both transmitter and receiver connectors. Using high-speed PLL technology, the TLK1221 serializes and transmits data along one differential pair.
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www.ti.com Introduction 1 Introduction The Texas Instruments (TI) TLK1221 SERDES Evaluation Module (EVM) board is used to evaluate the TLK1221 device (40-pin 6-mm x 6-mm QFN PowerPAD). The board enables the designer to connect 50-Ω parallel buses to both the transmitter and receiver parallel connectors. Using high-speed PLL technology, the TLK1221 serializes data and transmits this data along a differential pair. The receiver part of the device de-serializes and presents the data on the parallel bus.
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www.ti.com TLK1221 EVM Board Configuration The power planes are split three ways to provide power to different parts of the board. This prevents coupling of switching noise between the analog and digital sections of the TLK1221, and provides voltage isolation for power consumption testing. The VDD, VDDA, and VDDPLL connectors require a nominal 2.5V and are joined together by removable jumpers on headers JMP9 and JMP10 that are installed in the default configuration.
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www.ti.com Typical Test and Setup Configurations next to the RD and TD pins provide a convenient ground reference for a scope probe or coax cables. The additional TD row and VDD pins allow a static pattern to be driven into the TD bus by placing jumpers across either the TD and VDD pins for a HIGH, or TD and GND pins for a LOW eliminating the need for cables for quick tests. The extra row of TD can also be used to monitor the signals on the TD pins while simultaneously looping back into the RD pins.
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www.ti.com Typical Test and Setup Configurations (TD0-TD4 for DDR mode). The TLK1221 device serializes and presents the data on the high-speed serial pair (TXP/TXN). The serial TX data is then looped back to the receiver side and the device de-serializes and presents the data on the receiver side RD0–RD9 (RD0-RD4 for DDR mode). The data is received by the BERT and compared against the transmitted pattern and monitored for valid data and errors.
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www.ti.com Typical Test and Setup Configurations VDDA TXP RXP N TX VDD N RX VDD JMP9 VDDA VDDPLL JMP10 VDDPLL GND TLK1221 JMP7 PRBSEN SYNCEN ENABLE RBCMODE LOOPEN REFCLK GND GND JMP6 98 7 65 43 21 0 98 76 5 43 21 0 POWER SUPPLY JMP8 SYNC RBC1 RBC0 GND VDD GND RD[9:0] TD[9:0] GND TD[9:0] VDD CLOCK GENERATOR 2.5V + - PARALLEL ANALYZER RD[9:0] ANALYZER ANALYZER CLOCK Figure 5.
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www.ti.com Typical Test and Setup Configurations VDDA TXP RXP TX N N VDD X R VDD JMP9 VDDA VDDPLL JMP10 VDDPLL GND REFCLK TLK1221 JMP7 PRBSEN SYNCEN ENABLE RBCMODE LOOPEN GND GND JMP6 98 7 65 43 21 0 JMP8 SYNC RBC1 RBC0 GND VDD GND RD[9:0] TD[9:0] GND TD[9:0] VDD 98 76 5 43 21 0 PULSE GENERATOR CLOCK OUT POWER SUPPLY 2.5V + DIGITAL OSCILLOSCOPE CH1 CH2 CH3 CH4 Figure 6.
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www.ti.com Typical Test and Setup Configurations TX+/ANALYZER (PRBS 2^7-1) DIGITAL OSCILLOSCOPE CLOCK GENERATOR SERIAL BERT CH1 CH2 CH3 CH4 RX+/GENERATOR (PRBS 2^7-1) VDDA TXP TX VDD N RX VDD JMP9 VDDA VDDPLL - JMP10 + VDDPLL 2.5V RXP N POWER SUPPLY GND REFCLK TLK1221 JMP7 PRBSEN SYNCEN ENABLE RBCMODE LOOPEN GND GND JMP6 9 8 765 432 10 98 7 65 43 21 0 JMP8 SYNC RBC1 RBC0 GND VDD GND RD[9:0] TD[9:0] GND TD[9:0] VDD Figure 7.
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www.ti.com Schematic, Bill of Materials, and Board Layouts 5 Schematic, Bill of Materials, and Board Layouts 5.1 Schematic Figure 8. TLK1221 EVM Schematic The TLK1221 EVM schematic is shown on the following page.
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5 4 VDD 3 2 C27 C28 C29 0.01uF .01uf 0.1uf 1.0uf 0.01uF D + J2 68uf RXP R1 100 C31 + J3 RXP VDDPLL R8 1K C30 C3 TXN C4 10uf TXN D2 HSMB-C170 VDD P4 JMP6C J4 RXN RXN 0.01uF 0.01uF 1 1 C2 TXP 1 Header 2x1 1 C1 TXP P3 1 2 D J1 VDDPLL JMP9 2 GND VDDPLL VDDA C7 0.01uF SYNCEN PRBSEN 40 39 38 37 36 35 34 33 32 31 59 53 47 41 35 29 23 17 11 5 60 54 48 42 36 30 24 18 12 6 C6 0.
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www.ti.com Schematic, Bill of Materials, and Board Layouts 5.2 Bill of Materials Table 3. TLK1221 EVM Bill of Materials Item Qty Reference 1 8 C1–C4, C6, C7, C17, C18 0.01 μF Value 0603 CAP Part 06031C102JAT2A Part Number Avx Corporation Manufacturer 2 1 C16 100 pF 0603 CAP 06031A101JAT2A Avx Corporation 3 3 C22, C27, C32 1 μF 0603 CAP 0603YD105KAT2A Avx Corporation 4 1 C21 10 μF 0603 CAP GRM188R60G106ME47D Murata Electronics 5 1 C19 0.
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www.ti.com Schematic, Bill of Materials, and Board Layouts 5.3 Board Layouts 6492635 TLK1221 EVM REV. GND 5 6 7 7 8 9 8 9 LOO PEN E NABLE RBCMODE P RBSEN S YNCEN N VDD RBC0 4 5 6 TX VDD VDDA GND 4 G ND TD V DD 2 3 TD 1 2 3 TXP VDDPLL TD VDD SYNC G ND 0 1 GND 0 RD PIN 1 RD TD XN R RXP RBC1 GND REFCLK GND + VDD_LED VDDA_LED VDDPLL_LED + GND └ + PULL -UPS VDDA VDDPLL GND GND VDD Figure 9.
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www.ti.com Schematic, Bill of Materials, and Board Layouts Figure 10.
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www.ti.com Schematic, Bill of Materials, and Board Layouts Figure 11.
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www.ti.com Schematic, Bill of Materials, and Board Layouts Figure 12.
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www.ti.com Schematic, Bill of Materials, and Board Layouts Figure 13.
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www.ti.com Schematic, Bill of Materials, and Board Layouts Figure 14.
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www.ti.com Schematic, Bill of Materials, and Board Layouts Figure 15.
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www.ti.com Schematic, Bill of Materials, and Board Layouts Table 4. TLK1221 EVM PCB Layer Construction Subclass Name TOP L2_GND L3_SIG L4_GND L5_SIG/VDDPLL L6_GND L7_VDD/VDDA L8_GND L9_GND BOTTOM Type Thickness (MIL) Conductivity (mho/cm) Dielectric Constant Loss Tangent SURFACE AIR CONDUCTOR COPPER 2.4 595900 1 0 DIELECTRIC FR-4 4.5 0 4.1 0.035 PLANE COPPER 1.2 595900 1 0 DIELECTRIC FR-4 7.5 0 4.1 0.035 CONDUCTOR COPPER 1.2 595900 1 0 DIELECTRIC FR-4 7.
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EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.