Datasheet

TLK1211RCP
SLLS658D – SEPTEMBER 2006– REVISED APRIL 2011 www.ti.com
Terminal Functions (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
RBCMODE 32 I Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output
P/D
(1)
on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is
output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full
baud-rate clock is output on RBC0 and RBC1 is held low.
RBC0 31 O Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit
RBC1 30 output data on RD0–RD9. The operation of these clocks is dependent upon the receive clock
mode selected.
In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and
RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous
detect. The clocks are always expanded during data realignment and never slivered or truncated.
RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
In the normal rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is
aligned to the rising edge.
In the DDR mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned
on both the rising and falling edges.
RD0–RD9 45, 44, O Receive data. When in TBI mode (MODESEL = low), these outputs carry 10-bit parallel data
43, 41, output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and
40, 39, RBC1, depending on the receive clock mode selected. RD0 is the first bit received. When in the
38, 36, DDR mode (MODESEL = high), only RD0–RD4 are valid. RD5–RD9 are held low. The 5-bit
35, 34 parallel data is clocked out of the transceiver on the rising edge of RBC0.
REFCLK 22 I Reference clock. REFCLK is an external input clock that synchronizes the receiver and
transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input
data (TD0–TD9) for serialization. In the TBI mode that data is registered on the rising edge of
REFCLK.
In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the
most significant bits aligned on the rising edge of REFCLK.
RXP 54 PECL I Differential input receive. RXP and RXN together are the differential serial input interface from a
RXN 52 copper or an optical I/F module.
SYNCEN 24 I Synchronous function enable. When SYNCEN is high, the internal synchronization function is
P/U
(2)
activated. When this function is activated, the transceiver detects the K28.5 comma character
(0011111 negative beginning disparity) in the serial data stream and realigns data on byte
boundaries if required. When SYNCEN is low, serial input data is unframed in RD0–RD9.
SYNC/PASS 47 O Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in
the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In
PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of the PRBS test results
(high = pass).
TD0–TD9 2-4, 6-9, I Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data
11-13 output from a protocol device to the transceiver for serialization and transmission. This 10-bit
parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a
serial stream with TD0 sent as the first bit.
When in the DDR mode (MODESEL = high) only TD0–TD4 are valid. The 5-bit parallel data is
clocked into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial
stream with TD0 sent as the first bit.
TXP 62 PECL Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper
TXN 61 O or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high
and are active when LOOPEN is low.
TEST
ENABLE 28 I When this terminal is low, the device is disabled for Iddq testing. RD0–RD9, RBCn, TXP, and
P/U
(2)
TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When
ENABLE is high, the device operates normally.
JTDI 48 I Test data input. IEEE1149.1 (JTAG)
P/U
(2)
JTDO 27 O Test data output. IEEE1149.1 (JTAG)
JTMS 55 I Test mode select. IEEE1149.1 (JTAG)
P/U
(2)
JTRSTN 56 I Reset signal. IEEE1149.1 (JTAG)
P/U
(2)
(2) P/U = Internal pullup
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