Datasheet

2:1
MUX
PRBS
Generator
10 Bit
Registers
TD(0-9)
PRBSEN
LOOPEN
Parallel to
Serial
Phase Generator
Clock
REFCLK
Control
Logic
MODESEL
ENABLE
TESTEN
Interpolator
and
Clock Extraction
PRBS
Verification
Serial to Parallel
and
Comma Detect
Clock
RBC1
RBC0
SYNC/PASS
RD(0-9)
SYNCEN
RBCMODE
JTAG
Control
Register
JTMS
JTRSTN
JTDI
TCK
JTDO
2:1
MUX
2:1
MUX
Clock
Data
TXP
TXN
RXP
RXN
LOS
TLK1211RCP
www.ti.com SLLS658D – SEPTEMBER 2006– REVISED APRIL 2011
Table 1. AVAILABLE OPTIONS
(1)
PACKAGE
T
A
PLASTIC QUAD FLAT PACK (RCP)
–40°C to 85°C TLK1211RCP
(1) For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
BLOCK DIAGRAM
Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
SIGNAL
MODESEL 15 I Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR
P/D
(1)
interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode
is selected. The default mode is the TBI.
LOS 26 O Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.
If the magnitude of RXP-RXN > 150 mV, then LOS = 1 which is a valid input signal.
If the magnitude of RXP-RXN > 50 mV and < 150 mV, then LOS is undefined.
If the magnitude of RXP-RXN < 50 mV, then LOS = 0 which is a loss of signal.
Note: Above LOS conditions are specified only for Input Common Mode Voltage (RXP+RXN)/2 ≥
1.25V
(1) P/D = Internal pulldown
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