Datasheet

80%
50%
20%
t
r
t
r
t
f
t
f
80%
50%
20%
∼ V
∼ V
∼ V
∼ V
80%
20%
0 V
∼ 1V
∼ −1V
TX+
TX−
VOD
TLK1211RCP
SLLS658D – SEPTEMBER 2006– REVISED APRIL 2011 www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
V
OD
V
OD
= |TxD-TxN| R
t
= 50Ω 600 800 1100 mV
V
(cm)
Transmit common mode voltage range R
t
= 50Ω 1000 1250 1400 mV
Receiver input voltage requirement,
200 1600 mV
V
ID
= |RxP - RxN|
Receiver common mode voltage range, (RxP
1000 1250 2250 mV
+ RxN)/2
I
lkg(R)
Receiver input leakage current -350 350 μA
C
I
Receiver input capacitance 2 pF
Differential output jitter, Random +
deterministic, PRBS pattern, 0.24 UI
R
ω
= 125 MHz
t
(TJ)
Serial data total jitter (peak-to-peak)
Differential output jitter, Random +
deterministic, PRBS pattern, 0.2 UI
R
ω
= 106.25 MHz
Differential output jitter, PRBS pattern,
t
(DJ)
Serial data deterministic jitter (peak-to-peak) 0.10 UI
R
ω
= 125 MHz
R
L
= 50 Ω, C
L
= 5 pF, See Figure 8
t
r
, t
f
Differential signal rise, fall time (20% to 80%) 100 250 ps
and Figure 7
Differential input jitter, Random +
Serial data jitter tolerance minimum required
0.25 UI
deterministic, R
ω
= 125 MHz
eye opening, (per IEEE-802.3 specification at
1.25Gbps and per CPRI 2.0 specification at
Differential input jitter, Random + .4 UI
0.34 UI
614.4Mbps)
deterministic, R
ω
= 61.44MHz
Receiver data acquisition lock time from
500 μs
powerup
.75 UI jitter closure with random data
256 ns
@ 1.25 Gbps
Data re-lock time from application of valid
input data stream
.20 UI jitter closure with 01010.. data
128 ns
@ 1.25Gbps
TBI modes See Figure 1 20 22
t
d(Tx latency)
Tx latency UI
DDR mode 30 32
TBI modes See Figure 6 18 24
DDR mode 17 23
TBI mode 600–620 Mbps 18 21
t
d(Rx latency)
Rx latency UI
DDR mode 600–620 Mbps 17 22
TBI mode 1228.8 Mbps 19 23
DDR mode 1228.8 Mbps 18 23
(1) UI = serial bit time
Figure 7. Differential and Common-Mode Output Voltage Definitions
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