Datasheet

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DXX.X
K28.5
DXX.X
DXX.X K28.5
K28.5 DXX.X DXX.XDXX.X DXX.X
DXX.X
K28.5
DXX.X
DXX.X K28.5
K28.5 DXX.X DXX.X
31 Bit
Times
Max Receive
Path Latency
Worst Case
Misaligned K28.5
Misalignment Corrected
INPUT DATA
RBC0
RBC1
RD(0-9)
SYNC
Corrupt Data
30 Bit
Times (Max)
Data Reception Latency
RXP, RXN
RD(0−9)
RBC0
10-Bit Code
t
d(Rx latency)
10-Bit Code
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9
Loss of Signal Detection
TLK1201ARCP , TLK1201AIRCP
ETHERNET TRANSCEIVERS
SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007
Figure 5. Word Realignment Timing Characteristics Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the
SYNC pulse is present for the entire RBC0 period.
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times, and the
maximum latency is 31 bit times. The minimum latency in DDR mode is 27 bit times and maximum latency is 34
bit times.
Figure 6. Receiver Latency - TBI Normal Mode Shown
This device has a loss-of-signal (LOS) detection circuit for conditions where the incoming signal no longer has
sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication of gross
signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of signal
coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than 150 mV. The
LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined.
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