Datasheet

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TRANSMITTER/RECEIVER CHARACTERISTICS
80%
50%
20%
t
r
t
r
t
f
t
f
80%
50%
20%
∼ V
∼ V
∼ V
∼ V
80%
20%
0 V
∼ 1V
∼ −1V
TX+
TX−
VOD
TLK1201ARCP , TLK1201AIRCP
ETHERNET TRANSCEIVERS
SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1)
R
t
= 50 Ω 600 850 1100
V
OD
= |TxD-TxN| mV
R
t
= 75 Ω 800 1050 1200
R
t
= 50 Ω
V
(cm)
Transmit common mode voltage range 1100 1250 1400 mV
R
t
= 75 Ω
Receiver input voltage requirement,
200 1600 mV
V
ID
= |RxP - RxN|
Receiver common mode voltage range, (RxP
1000 1250 2250 mV
+ RxN)/2
I
lkg(R)
Receiver input leakage current -350 350 μ A
C
I
Receiver input capacitance 2 pF
Differential output jitter, Random +
deterministic, PRBS pattern, 0.24 UI
R
ω
= 125 MHz
t
(TJ)
Serial data total jitter (peak-to-peak)
Differential output jitter, Random +
deterministic, PRBS pattern, 0.2 UI
R
ω
= 106.25 MHz
Differential output jitter, PRBS pattern,
t
(DJ)
Serial data deterministic jitter (peak-to-peak) 0.10 UI
R
ω
= 125 MHz
t
r
, t
f
Differential signal rise, fall time (20% to 80%) R
L
= 50 Ω , C
L
= 5 pF, See Figure 7 100 250 ps
Differential input jitter, Random +
0.25 UI
deterministic, R
ω
= 125 MHz
Serial data jitter tolerance minimum required
Differential input jitter, random +
eye opening, (per IEEE-802.3 specification)
determinisitc, PRBS pattern at zero 0.3 UI
crossing
Receiver data acquisition lock time from
500 μ s
powerup
Data relock time from loss of synchronization 1024 Bit times
TBI modes See Figure 1 19 20
t
d(Txlatency)
Tx latency UI
DDR mode 29 30
TBI modes See Figure 6 20 31
DDR mode 27 34
TBI mode 600 – 620 Mbps 24 28
t
d(Rxlatency)
Rx latency UI
DDR mode 600 – 620 Mbps 27 31
TBI mode 1228.8 Mbps 25 29
DDR mode 1228.8 Mbps 27 33
(1) UI = serial bit time
Figure 7. Differential and Common-Mode Output Voltage Definitions
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