Datasheet

Idle
(J/K)
Data
(TR)
Data
t
5
t
4
t
2
t
3
t
1
t
2
t
2
t
2
PMD
Input Pair
XI
RX_DV
CRS_DV
RXD[1:0]
RX_ER
t
7
t
6
t
7
t
7
RX_CLK
TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
9.7.24 RMII Receive Timing
Table 9-24. RMII Receive Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
XI Clock Period 50MHz Reference Clock 20
ns
t
2
RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from XI rising 4 10.8 14
From JK symbol on PMD
t
3
CRS ON delay Receive Pair to initial 17.6
assertion of CRS_DV
From TR symbol on PMD
t
4
CRS OFF delay Receive Pair to initial 26.2 bits
assertion of CRS_DV
From symbol on Receive
t
5
RXD[1:0] and RX_ER latency Pair. * Elasticity buffer set 29.7
to default value (01)
50MHz “Recovered clock”
t
6
RX_CLK Clock Period while working in “RMII 20
receive clock” mode
ns
RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from RX_CLK While working in “RMII
t
7
3.8
rising receive clock” mode
Figure 9-24. RMII Receive Timing
NOTE
1. Per the RMII Specification, output delays assume a 25pF load.
2. CRS_DV is asserted asynchronously in order to minimize latency of control signals
through the PHY. CRS_DV may toggle synchronously at the end of the packet to indicate
CRS de-assertion.
3. RX_DV is synchronous to XI. While not part of the RMII specification, this signal is
provided to simplify recovery of receive data.
4. “RMII receive clock” mode is not part of the RMII specification that allows synchronization
of the MAC-PHY RX interface in RMII mode. Setting register 0x000A bit [0] is required to
activate this mode.
94 Electrical Specifications Copyright © 2011–2014, Texas Instruments Incorporated
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