Datasheet

t
1
t
2
t
3
t
4
ValidData
Symbol
XI
TXD[1:0]
TX_EN
PMDOutputPair
TX_CLK
TX_EN
TXD[3:0]
CRS
RX_CLK
RX_DV
RXD[3:0]
T0362-01
t
1
TLK110
www.ti.com SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
9.7.22 10Mbs Internal Loopback Timing
Table 9-22. 10Mbs Internal Loopback Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
TX_EN to RX_DV Loopback 10Mbs internal loopback mode 1.7 μs
(1) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
(2) Analog loopback was used. Looping the TX to RX at the analog input/output stage.
Figure 9-22. 10Mbs Internal Loopback Timing
9.7.23 RMII Transmit Timing
Table 9-23. RMII Transmit Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
50MHz Reference
t
1
XI Clock Period 20
Clock
t
2
TXD[1:0] and TX_EN data setup to X1 rising 1.4
ns
VDD_IO = 3.3V 2.0
t
3
TXD[1:0] and TX_EN data hold to X1 rising
VDD_IO = 2.5V 4.9
t
4
XI Clock to PMD Output Pair Latency 12 bits
Figure 9-23. RMII Transmit Timing
Copyright © 2011–2014, Texas Instruments Incorporated Electrical Specifications 93
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