Datasheet

PMDInputPair
SD+Intermal
T0360-01
t
1
t
2
FastLinkPulse(s)
Clock
Pulse
Data
Pulse
Clock
Pulse
FLP Burst FLP Burst
T0359-01
t
1
t
2
t
3
t
3
t
4
t
5
TLK110
www.ti.com SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
9.7.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 9-19. Auto-Negotiation Fast Link Pulse (FLP) Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Clock Pulse to Clock Pulse Period 125 μs
t
2
Clock Pulse to Data Pulse Period Data = 1 62 μs
t
3
Clock, Data Pulse Width 114 ns
t
4
FLP Burst to FLP Burst Period 16 ms
t
5
Burst Width 2 ms
Figure 9-19. Auto-Negotiation Fast Link Pulse (FLP) Timing
9.7.20 100Base-TX Signal Detect Timing
Table 9-20. 100Base-TX Signal Detect Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
SD Internal Turn-on Time 100 μs
t
2
Internal Turn-off Time 200 μs
NOTE: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
Figure 9-20. 100Base-TX Signal Detect Timing
Copyright © 2011–2014, Texas Instruments Incorporated Electrical Specifications 91
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