Datasheet

RX_CLK
Valid Data
RXD[3:0]
RX_DV
T0349-01
t
1
t
2
t
4
t
3
TX_CLK
Valid Data
TXD[3:0]
TX_EN
t
1
t
3
t
4
t
2
TLK110
www.ti.com SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
9.7.11 10Mbs MII Transmit Timing
Table 9-11. 10Mbs MII Transmit Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
TX_CLK Low Time
10Mbs MII mode 190 200 210 ns
t
2
TX_CLK High Time
t
3
TXD[3:0], TX_EN Data Setup to TX_CLK ↑ 10Mbs MII mode 25 ns
t
4
TXD[3:0], TX_EN Data Hold from TX_CLK ↑ 10Mbs MII mode 0 ns
An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown in
Figure 9-11, the MII signals are sampled on the falling edge of TX_CLK.
Figure 9-11. 10Mbs MII Transmit Timing
9.7.12 10Mb/s MII Receive Timing
Table 9-12. 10Mb/s MII Receive Timing
PARAMETER
(1)
TEST CONDITIONS MIN TYP MAX UNIT
t
1
RX_CLK High Time
160 200 240 ns
t
2
RX_CLK Low Time
t
3
RX_CLK rising edge delay from RXD[3:0], RX_DV Valid 10Mbs MII mode 100 ns
t
4
RX_CLK to RXD[3:0], RX_DV Delay 10Mbs MII mode 100 ns
(1) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
Figure 9-12. 10Mb/s MII Receive Timing
Copyright © 2011–2014, Texas Instruments Incorporated Electrical Specifications 87
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