Datasheet

TX_CLK
TXD
TX_EN
PMD Output Pair
(T/R)DATA IDLE
(T/R)
DATA
IDLE
T0344-01
t
1
TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
9.7.7 100Base-TX Transmit Packet Deassertion Timing
Table 9-7. 100Base-TX Transmit Packet Deassertion Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
TX_CLK to PMD Output Pair deassertion 100Mbs Normal mode 4.6 bits
Figure 9-7. 100Base-TX Transmit Packet Deassertion Timing
84 Electrical Specifications Copyright © 2011–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLK110