Datasheet

TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
3.1 Bootstrap Configuration
Bootstrap configuration is a convenient way to configure the TLK110 into specific modes of operation.
Some of the functional pins are used as configuration inputs. The logic states of these pins are sampled
during reset and are used to configure the device into specific modes of operation. The table below
describes bootstrap configuration.
A 2.2kΩ resistor is used for pull-down or pull-up to change the default configuration. If the default option is
desired, then there is no need for external pull-up or pull down resistors. Because these pins may have
alternate functions after reset is deasserted, they must not be connected directly to VCC or GND.
PIN TYPE
NAME NO. DESCRIPTION
PHYAD0 (COL) 42 PHY Address [4:0]: The TLK110 provides five PHY address pins, the states of which are latched
PHYAD1 (RXD_0) 43 into an internal register at system hardware reset. The TLK110 supports PHY Address values 0
S, O, PD /
PHYAD2 (RXD_1) 44 (<00000>) through 31 (<11111>). PHYAD[4:1] pins have weak internal pull-down resistors, and
PU
PHYAD3 (RXD_2) 45 PHYAD[0] has weak internal pull-up resistor, setting the default PHYAD if no external resistors
PHYAD4 (RXD_3) 46 are connected.
Software Strapping Mode: The TLK110 provides a mechanism to extend the number of
configuration pins to allow wider system programmability of PHY functions. An external pull-down
will cause the device to enter SW Strapping Mode. In this mode the device will wake up after
Power-up or Reset in Power-Down mode, this will allow the system processor to access
SW_STRAP 21 I
dedicated Strapping Registers and configure modes of operation. An access to SW Strapping
Mode Release register must be done to take the device out of power-down mode. See
Section 3.8 for more details. An external pull-up resistor should be used to disable Software
Strapping Mode.
AN_EN: A high level on this pin puts the part into advertised Auto-Negotiation mode with the
capability set by AN_0 and AN_1 pins. A low level on AN_EN puts the part into Forced Mode with
the capability set by AN_0 and AN_1 pins.
AN_0, AN_1: These input pins control the forced or advertised operating mode according to the
following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1)
through 2.2kΩ resistors. DO NOT connect these pins directly to GND or VCC.
The states of these pins are latched into the Basic Mode Control Register and the
Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 because these pins have internal pull-ups.
AN_EN
AN_EN AN_1 AN_0 Forced Mode
(LED_ACT) 26
0 0 0 10Base-T, Half-Duplex
AN_1 27 S, O, PU
(LED_SPEED) 28
0 0 1 10Base-T, Full-Duplex
AN_0 (LED_LINK)
0 1 0 100Base-TX, Half-Duplex
0 1 1 100Base-TX, Full-Duplex
AN_EN AN_1 AN_0 Advertised Mode
1 0 0 10Base-T, Half or Full-Duplex
1 0 1 100Base-TX, Half or Full-Duplex
10Base-T, Half-Duplex
1 1 0
100Base-TX, Half-Duplex
10Base-T, Half orFull-Duplex
1 1 1
100Base-TX, Half or Full-Duplex
LED Configuration: This option, along with the LEDCR register bit, selects the mode of
LED_CFG (CRS) 40 S, O, PU operation of the LED pins. Default is Mode 1. All modes are also configurable via register access.
See PHY Control Register (PHYCR), Address 0x0019
AMDIX_EN Auto-MDIX Enable: This option sets the Auto-MDIX mode. By default, it enables Auto-MDIX. An
41 S, O, PU
(RX_ER) external pull-down resistor disables Auto-MDIX mode.
MII Mode Select: This option selects the operating mode of the MAC data interface. This pin has
MII_MODE
39 S, O, PD a weak internal pull-down, and it defaults to normal MII operation mode. An external pull-up
(RX_DV)
causes the device to operate in RMII mode.
8 Hardware Configuration Copyright © 2011–2014, Texas Instruments Incorporated
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