Datasheet

TLK110
www.ti.com SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
8.3 PHY Reset Control Register (PHYRCR)
Table 8-32. PHY Reset Control Register (PHYRCR), address 0x001F
BIT NAME DEFAULT FUNCTION
15 Software Reset 0, RW,SC Software Reset:
1 = Reset PHY. This bit is self cleared and has same effect as Hardware reset pin.
0 = Normal Operation
14 Software 0, RW,SC Software Restart:
Restart 1 = Reset PHY. This bit is self cleared and resets all PHY circuitry except the registers.
0 = Normal Operation
13:0 RESERVED 00 0000 0000 Writes ignored, read as 0
0000, RO
8.4 TX_CLK Phase Shift Register (TXCPSR)
This register allows programming the phase of the MII transmit clock (TX_CLK pin). The TX_CLK has a
fixed phase to the XI pin. However the default phase, while fixed, may not be ideal for all systems,
therefore this register may be used by the system to align the reference clock (XI pin) to the TX_CLK. The
phase shift value is in 4ns units. The phase shift value should be between 0 and 10 (0ns to 40ns). If value
greater than 10 is written, the update value will be the written value modulo 10.
Table 8-33. TX_CLK Phase Shift Register (TXCPSR), address 0x0042
BIT NAME DEFAULT FUNCTION
15:5 RESERVED 0000 0000 RESERVED: Writes ignored, read as 0
000, RO
4 Phase Shift 0,RW,SC TX Clock Phase Shift Enable:
Enable 1 = Perform Phase Shift to the TX_CLK according to the value written to Phase Shift Value in bits
[4:0].
0 = No change in TX Clock phase
3:0 Phase Shift 0000,RW TX Clock Phase Shift Value:
Value The value of this register represents the current phase shift between Reference clock at XI and MII
Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4
times the difference (in nSec).
For example, if the value of this register is 0x2, Writing 0x9 to this register shifts TX_CLK by 28nS (4
times 7).However, since the maximum difference between XI and TX_CLK could be 40nSec (value of
10) in case of writing value bigger than 10, the updated value is the written value modulo 10.
8.5 Power Back Off Control Register (PWRBOCR)
Table 8-34. Power Back Off Control Register (PWRBOCR), address 0x00AE
BIT NAME DEFAULT FUNCTION
15 RESERVED 1, RO RESERVED
14 RESERVED 0, RO RESERVED
13:9 RESERVED 00 000, RO RESERVED
8:6 Power Back 0, RW Power Back Off Level: See Application Note SLLA328
Off 000 = Normal Operation
001 = Level 1 (up to 5m cable between TLK link partners)
010 = Level 2 (up to 80m cable between TLK link partners)
011 = Level 3 (up to 100m cable between TLK link partners)
Others = Reserved
5:0 RESERVED 10 0000, RO RESERVED
8.6 Voltage Regulator Control Register (VRCR)
This register gives the host processor the ability to power down the voltage-regulator block of the PHY via
register access. This power-down operation is available in systems operating with an external power
supply.
Copyright © 2011–2014, Texas Instruments Incorporated Register Block 71
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