Datasheet

TLK110
www.ti.com SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
PIN
TYPE DESCRIPTION
NAME NO.
JTAG_TMS 10 I, PU JTAG Test Mode Select: This pin has a weak internal pullup.
JTAG_TRST 11 I, PU JTAG Reset: This pin is an active-low asynchronous test reset with a weak internal pullup.
2.8 Reset and Power Down
PIN
TYPE DESCRIPTION
NAME NO.
This pin is an active-low reset input that initializes or re-initializes all the internal registers of the
RESET 29 I, PU TLK110. Asserting this pin low for at least 1µs will force a reset process to occur. All jumper
options are reinitialized as well.
Register access is required for this pin to be configured either as power down or as an interrupt.
The default function of this pin is power down.
When this pin is configured for a power down function, an active low signal on this pin places the
INT / PWDN 7 IO, OD, PU device in power down mode.
When this pin is configured as an interrupt pin, then this pin is asserted low when an interrupt
condition occurs. The pin has an open-drain output with a weak internal pull-up. Some
applications may require an external pull-up resistor.
2.9 Power and Bias Connections
PIN
TYPE DESCRIPTION
NAME NO.
RBIAS 24 I Bias Resistor Connection: Use a 4.87kΩ 1% resistor connected from RBIAS to GND.
PFBOUT 23 O Power Feedback Output: Place 10µf and 0.1μF capacitors (ceramic preferred) close to PFBOUT.
In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 18 and pin 37). See Figure 3-1
for proper placement.
In multiple supply operation, this pin is not used.
Power Feedback Input: These pins are fed with power from PFBOUT (pin 23) in single supply
PFBIN1 18
operation.
I
In multiple supply operation, connect a 1.55V external power supply to these pins. Connect a small
PFBIN2 37 capacitor of 0.1µF close to each pin. To power down the internal linear regulator, write to register
0x00d0.
VDD_IO 32, 48 P I/O 3.3V, 2.5V, or 1.8V Supply - For details, see Section 3.2.3
IOGND 35, 47 P I/O ground
DGND 36 P Digital ground
AVDD33 22 P Analog 3.3V power supply
AGND 15, 19 P Analog ground
RESERVED 20 I/O RESERVED: This pin must be pulled-up through 2.2kΩ resistor to AVDD33 supply.
3 Hardware Configuration
This section includes information on the various configuration options available with the TLK110. The
configuration options described below include:
• Bootstrap Configuration • PHY Address
• Power Supply Configuration • Software Strapping Mode
• IO Pins Hi-Z State During Reset • LED Interface
• Auto-Negotiation • Loopback Functionality
• Auto-MDIX • BIST
• MII Isolate mode • Cable Diagnostics
Copyright © 2011–2014, Texas Instruments Incorporated Hardware Configuration 7
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