Datasheet

TLK110
www.ti.com SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
Table 8-27. PHY Control Register (PHYCR), address 0x0019 (continued)
BIT NAME DEFAULT DESCRIPTION
11 MI Link 0, RO MII Link Status:
Status 1 = 100BT Full-duplex Link is active and it was established using Auto-Negotiation
0 = No active link of 100BT Full-duplex, established using Auto-Negotiation
10:8 RESERVED 000, RO RESERVED: Writes ignored, read as 0.
7 Bypass LED 0, RW Bypass LED Stretching:
Stretching 1 = Bypass LED stretching
0 = Normal LED operation
Set this bit to 1 to bypass the LED stretching; the LEDs reflect the internal value.
6:5 LED CFG 0, RW LED Configuration Modes:
0, RW,
Mode LED_CFG[1] LED_CFG[0] LED_LINK LED_SPEED LED_ACT
Pin_Strap,
SWSC_Strap
1 Don't Care 1 ON for Good Link ON Pulse for Activity
OFF for No Link OFF for No Activity
2 0 0 ON in 100 Mb/s ON for Collision
OFF in 10 Mb/s OFF for No Collision
ON for Good Link
BLINK for Activity
3 1 0 ON for Full Duplex
OFF for Half Duplex
4:0 PHY ADDR 0000 1, RO PHY Address:
Strapping configuration for PHY Address.
8.1.24 10Base-T Status/Control Register (10BTSCR)
This register provides the ability to control and read status of the PHY’s internal 10Base-T functionality.
Table 8-28. 10Base-T Status/Control Register (10BTSCR), address 0x001A
BIT NAME DEFAULT DESCRIPTION
15:14 RESERVED 000, RO RESERVED: Writes ignored, read as 0.
13 Receiver TH 0, RW Lower Receiver Threshold Enable:
1 = Enable 10Base-T lower receiver threshold to allow operation with longer cables
0 = Normal 10Base-T operation
12:9 Squelch 0000, RW Squelch Configuration:
Used to set the Peak Squelch ‘ON’ threshold for the 10Base-T receiver. Every step is equal to
50mV and allow raising/lowering the Squelch threshold from 200mV to 600mV. The default
Squelch threshold is set to 200mV.
8 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
7 NLP Disable 0, RW NLP Transmission Control:
1 = Disable transmission of NLPs
0 = Enable transmission of NLPs
6:5 RESERVED 00, RO RESERVED: Writes ignored, read as 0.
4 Polarity Status 0, RO 10Mb Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
This bit is a duplication of bit 12 in the PHYSTS register (0x0010). Both bits will be cleared
upon a read of 10BTSCR register, but not upon a read of the PHYSTS register.
3:1 RESERVED 000, RO RESERVED: Writes ignored, read as 0.
0 Jabber Disable 0, RW Jabber Disable:
1 = Jabber function disabled
0 = Jabber function enabled
Note: This function is applicable only in 10Base-T
Copyright © 2011–2014, Texas Instruments Incorporated Register Block 69
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