Datasheet

TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
8.1.22 LED Control Register (LEDCR)
This register provides the ability to directly manually control any or all LED outputs.
Table 8-26. LED Control Register (LEDCR), address 0x0018
BIT NAME DEFAULT DESCRIPTION
15:11 RESERVED 0000 0, ro RESERVED: Writes ignored, read as 0.
10:9 Blink Rate 10, RW LED Blinking Rate (ON/OFF duration):
00 = 20Hz (50mSec)
01 = 10Hz (100mSec)
10 = 5Hz (200mSec)
11 = 2Hz (500mSec)
8 LED Speed Polarity 0, RW, LED Speed Polarity Setting:
Pin_Strap 1 = Active High polarity setting
0 = Active Low polarity setting
Speed LED’s polarity defined by strapping value of this pin. This register allows
override of this strapping value.
7 LED Link Polarity 0, RW, LED Link Polarity Setting:
Pin_Strap 1 = Active High polarity setting
0 = Active Low polarity setting
Link LED polarity defined by strapping value of this pin. This register allows
override of this strapping value.
6 LED Active Polarity 0, RW, LED Activity Polarity Setting:
Pin_Strap 1 = Active High polarity setting
0 = Active Low polarity setting
Activity LED’s polarity defined by strapping value of this pin. This register allows
override of this strapping value.
5 Drive Speed LED 0,RW Drive LED Speed to the forced On/Off setting defined in bit 2:
1 = Drive value of On/Off bit onto LED_SPEED output pin
0 = Normal operation
4 Drive Link LED 0, RW Drive LED Link to the forced On/Off setting defined in bit 1:
1 = Drive value of On/Off bit onto LED_LINK output pin
0 = Normal operation
3 Drive Active LED 0,RW Drive LED Activity to the forced On/Off setting defined in bit 0:
1 = Drive value of On/Off bit onto LED_ACT output pin
0 = Normal operation
2 Speed LED On/Off Setting 0, RW Value to force on Speed LED output
1 Link LED On/Off Setting 0, RW Value to force on Link LED output
0 Act LED On/Off Setting 0, RW Value to force on Activity LED output
8.1.23 PHY Control Register (PHYCR)
This register provides the ability to control and set general functionality inside the PHY.
Table 8-27. PHY Control Register (PHYCR), address 0x0019
BIT NAME DEFAULT DESCRIPTION
15 Auto MDI/X 1, RW, Auto-MDIX Enable:
Enable Pin_Strap 1 = Enable Auto-negotiation Auto-MDIX capability
0 = Disable Auto- negotiation Auto-MDIX capability
14 Force MDI/X 0, RW Force MDIX:
1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair)
0 = Normal operation. (Transmit on TPTD pair, Receive on TPRD pair)
13 Pause RX 0, RO Pause Receive Negotiated Status: Indicates that pause receive should be enabled in the MAC.
Status Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause
Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
12 Pause TX 0,RO Pause Transmit Negotiated Status:
Status Indicates that pause transmit should be enabled in the MAC. Based on bits [11:10] in ANAR register
and bits [11:10] in ANLPAR register settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause
Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
68 Register Block Copyright © 2011–2014, Texas Instruments Incorporated
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