Datasheet

TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
Table 8-20. MII Interrupt Status Register 1 (MISR1), address 0x0012 (continued)
BIT NAME DEFAULT DESCRIPTION
11 Duplex Mode Changed INT 0,RO, COR Change of duplex status interrupt:
1 = Duplex status change interrupt is pending
0 = No change of duplex status
10 Auto-Negotiation Completed INT 0,RO, COR Auto-Negotiation Complete interrupt:
1 = Auto-negotiation complete interrupt is pending.
0 = No Auto-negotiation complete event is pending
9 FC HF INT 0,RO, COR False Carrier Counter half-full interrupt:
1 = False carrier counter (Register FCSCR, address 0x0014) exceeds half-
full interrupt is pending
0 = False carrier counter half-full event is not pending
8 RE HF INT 0,RO, COR Receive Error Counter half-full interrupt:
1 = Receive error counter (Register RECR, address 0x0015) exceeds half
full interrupt is pending
0 = No Receive error counter half full event pending
7:6 RESERVED 00, RO RESERVED: Writes ignored, read as 0.
5 Link Status Changed EN 0, RW Enable Interrupt on change of link status
4 Speed Changed EN 0, RW Enable Interrupt on change of speed status
3 Duplex Mode Changed EN 0, RW Enable Interrupt on change of duplex status
2 Auto-Negotiation Completed EN 0, RW Enable Interrupt on Auto-negotiation complete event
1 FC HF EN 0, RW Enable Interrupt on False Carrier Counter Register half-full event
0 RE HF EN 0, RW Enable Interrupt on Receive Error Counter Register half-full event
8.1.17 MII Interrupt Status Register 2 (MISR2)
This register contains events status and enables for the interrupt function. If an event has occurred since
the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the
register is set, an interrupt will be generated if the event occurs. The PHYSCR register (0x0011) bits 1 and
0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt
is not enabled.
Table 8-21. MII Interrupt Status Register 2 (MISR2), address 0x0013
BIT NAME DEFAULT DESCRIPTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14 AN Error INT 0,RO, COR Auto-Negotiation Error Interrupt:
1 = Auto-negotiation error interrupt is pending
0 = No Auto-negotiation error event pending
13 Page Rec INT 0,RO, COR Page Receive Interrupt:
1 = Page has been received
0 = Page has not been received
12 Loopback FIFO OF/UF INT 0,RO, COR Loopback FIFO Overflow/Underflow Event Interrupt:
1 = FIFO Overflow/Underflow event interrupt pending
0 = No FIFO Overflow/Underflow event pending
11 MDI Crossover Changed INT 0,RO, COR MDI/MDIX Crossover Status Changed Interrupt:
1 = MDI crossover status changed interrupt is pending
0 = MDI crossover status has not changed
10 Sleep Mode INT 0,RO, COR Sleep Mode Event Interrupt:
1 = Sleep Mode event interrupt is pending
0 = No sleep mode event pending
9 Polarity Changed INT 0,RO, COR Polarity Changed Interrupt:
1 = Data polarity changed interrupt pending
0 = No Data polarity event pending
8 Jabber Detect INT 0,RO Jabber Detect Event Interrupt:
1 = Jabber detect event interrupt pending
0 = No Jabber detect event pending
7 RESERVED 0,RW RESERVED: Writes ignored, read as 0
6 AN Error EN 0,RW Enable Interrupt on Auto-Negotiation error event
64 Register Block Copyright © 2011–2014, Texas Instruments Incorporated
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