Datasheet

TLK110

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SLLS901D –DECEMBER 2011–REVISED JANUARY 2014

Table 8-18. PHY Status Register (PHYSTS), address 0x0010 (continued)

BIT NAME DEFAULT DESCRIPTION

This bit will be cleared upon a read of the FCSR register.

10 Signal Detect 0,RO/LL Signal Detect:

Active high 100Base-TX unconditional Signal Detect indication from PMD

9 Descrambler 0,RO/LL Descrambler Lock:

Lock

Active high 100Base-TX Descrambler Lock indication from PMD

8 Page 0,RO Link Code Word Page Received:

Received

1 = A new Link Code Word Page has been received. This bit is a duplicate of Page Received (bit 1)

in the ANER register and it is cleared on read of the ANER register (0x0006).

0 = Link Code Word Page has not been received.

This bit will not be cleared upon a read of the PHYSTS register.

7 MII Interrupt 0,RO MII Interrupt Pending:

1 = Indicates that an internal interrupt is pending. Interrupt source can be determined by reading the

MISR Register (0x0012). Reading the MISR will clear this Interrupt bit indication.

0 = No interrupt pending

6 Remote Fault 0,RO Remote Fault:

1 = Remote Fault condition detected. Fault criteria: notification from Link Partner of Remote Fault

via Auto-Negotiation. Cleared on read of BMSR register (0x0001) or by reset.

0 = No remote fault condition detected

5 Jabber Detect 0,RO Jabber Detect:

1 = Jabber condition detected. This bit has meaning only in 10 Mb/s mode. This bit is a duplicate of