Datasheet

TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
8.1.13.1 Register Control Register (REGCR)
This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the
device address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate
MMD. REGCR also contains selection bits for auto increment of the data register. This register contains
the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register.
REGCR also contains selection bits (15:14) for the address auto-increment mode of ADDAR.
Table 8-16. Register Control Register (REGCR), address 0x000D
BIT BIT NAME DEFAULT DESCRIPTION
15:14 Function 0, RW 00 = Address
01 = Data, no post increment
10 = Data, post increment on read and write
11 = Data, post increment on write only
13:5 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
4:0 DEVAD 0, RW Device Address: In general, these bits [4:0] are the device address DEVAD that directs any
accesses of ADDAR register (0x000E) to the appropriate MMD. Specifically, the TLK110 uses the
vendor specific DEVAD [4:0] = “11111” for accesses. All accesses through registers REGCR and
ADDAR should use this DEVAD. Transactions with other DEVAD are ignored.
8.1.13.2 Address or Data Register (ADDAR)
This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register
(0x000D) to provide the access by indirect read/write mechanism to the extended register set.
Table 8-17. Data Register (ADDAR), address 0x000E
BIT BIT NAME DEFAULT DESCRIPTION
15:0 Addr/data 0, RW If REGCR register 15:14 = 00, holds the MMD DEVAD's address register, otherwise holds the
MMD DEVAD's data register
8.1.14 PHY Status Register (PHYSTS)
This register provides quick access to commonly accessed PHY control status and general information.
Table 8-18. PHY Status Register (PHYSTS), address 0x0010
BIT NAME DEFAULT DESCRIPTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14 MDI-X Mode 0,RO MDI-X mode as reported by the Auto-Negotiation state machine:
1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair)
This bit will be affected by the settings of the AMDIX_EN and FORCE_MDIX bits in the PHYCR
register. When MDIX is enabled, but not forced, this bit will update dynamically as the Auto-MDIX
algorithm swaps between MDI and MDI-X configurations.
13 Receive Error 0,RO/LH Receive Error Latch:
Latch
1 = Receive error event has occurred since last read of RXERCNT register (0x0015)
0 = No receive error event has occurred
This bit will be cleared upon a read of the RECR register
12 Polarity Status 0,RO Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
This bit is a duplication of bit 4 in the 10BTSCR register (0x001A). This bit will be cleared upon a read
of the 10BTSCR register, but not upon a read of the PHYSTS register.
11 False Carrier 0,RO/LH False Carrier Sense Latch:
Sense Latch
1 = False Carrier event has occurred since last read of FCSCR register (0x0014)
0 = No False Carrier event has occurred
60 Register Block Copyright © 2011–2014, Texas Instruments Incorporated
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