Datasheet

TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
8.1.11 Software Strap Control register 2 (SWSCR2)
This register contains the configuration bits used as strapping options or virtual strapping pins during HW
RESET. These configuration values are programmed by the system processor after HW_RESET/POR,
and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An
internal reset pulse is generated and the SW Strap bit values are latched into internal registers.
Table 8-14. SW Strap Control register 2 (SWSCR2), address 0x000A
BIT BIT NAME DEFAULT DESCRIPTION
15:14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
13:7 RESERVED 0, SWS, RW RESERVED
6 Fast Link-Up in 0, SWS, RW Fast Link-Up in Parallel Detect Mode:
Parallel Detect
1 = Enable Fast Link-Up time During Parallel Detection
0 = Normal Parallel Detection link establishment
In Fast Auto MDI-X and in Robust Auto MDI-X modes (bits 6 and 5 in register SWSCR1),
this bit is automatically set.
5 Extended FD 0, SWS, RW Extended Full-Duplex Ability:
Ability
1 = Force Full-Duplex while working with link partner in forced 100B-TX. When the
PHY is set to Auto-Negotiation or Force 100B-TX and the link partner is operated
in Force 100B-TX, the link is always Full Duplex
0 = Disable Extended Full Duplex Ability. Decision to work in Full Duplex or Half
Duplex mode follows IEEE specification.
4 Enhanced LED 0, SWS, RW Enhanced LED Link Functionality:
Link
1 = LED Link is ON only when link is established in 100B-TX Full Duplex mode.
0 = LED Link is ON when link is established.
3 Isolate MII in 0, SWS, RW Isolate MII outputs when FD Link @ 100BT is not achievable:
100BT HD
1 = When HD link established in 100B-TX MII outputs are isolated
0 = Normal MII outputs operation
2 RXERR During 1, SWS, RW Detection of Receive Symbol Error During IDLE State:
IDLE
1 = Enable detection of Receive symbol error during IDLE state
0 = Disable detection of Receive symbol error during IDLE state.
1 Odd-Nibble 0, SWS, RW Detection of Transmit Error:
Detection
1 = Disable detection of transmit error in odd-nibble boundary
Disable
0 = Enable detection of de-assertion of TX_EN on an odd-nibble boundary. In this case
TX_EN is extended by one additional TX_CLK cycle and behaves as if TX_ER
were asserted during that additional cycle.
0 RMII Receive 0, SWS, RW RMII Receive Clock:
Clock
1 = RMII Data (RXD [1:0]) is sampled and referenced to RX_CLK
0 = RMII Data (RXD [1:0]) is sampled and referenced to XI
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