Datasheet

TLK110
www.ti.com SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
Table 8-13. SW Strap Control register 1 (SWSCR1), address 0x0009 (continued)
BIT BIT NAME DEFAULT DESCRIPTION
3:2 Fast AN Sel 0, SWS, RW Fast Auto-Negotiation Select bits:
Fast AN Break Link Fail Auto-Neg Wait Timer
Select Link Inhibit
Timer Timer
<00> 80 50 35
<01> 120 75 50
<10> 240 150 100
<11> NA NA NA
Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs. In
Fast AN mode, both PHYs should be configured to the same configuration. These 2 bits
define the duration for each state of the Auto Negotiation process according to the table
above. The new duration time must be enabled by setting “Fast AN En” - bit 4 of this
register. Note: Using this mode in cases where both link partners are not configured to
the same Fast Auto-negotiation configuration might produce scenarios with unexpected
behavior.
1 Fast RXDV 0, SWS, RW Fast RXDV Detection:
Detection
1 = Enable assertion high of RX_DV on receive packet due to detection of /J/ symbol
only. If a consecutive /K/ does not appear, RX_ER is generated.
0 = Disable Fast RX_DV detection. The PHY operates in normal mode - RX_DV
assertion after detection of /J/K/.
0 INT OE 0, SWS, RW INT/PWDN Enable:
1 = INT/PWDN Pin is an open-drain Interrupt Output.
0 = INT/PWDN Pin is active-low Power Down input.
RESET (applied after SW Strap Config. finishes) latches the value of this register bit to bit
0 of the PHYSCR register (0x0011); this defines the PHYSCR[0] value. The INT OE bit,
as opposed to other SWSC bits, has no external pin to determine the default value. The
INT OE default value is always zero, unless changed during SW strap configuration mode.
Copyright © 2011–2014, Texas Instruments Incorporated Register Block 57
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