Datasheet
DGND
IOGND
XI
XO
VDD_IO
MDC
MDIO
LED_LINK/AN_0
LED_SPEED/AN_1
LED_ACT/COL/AN_EN
CLK_OUT
RBIAS
PFBOUT
AVDD33
SW_STRAP
RESERVED
AGND
PFBIN1
TD +
TD –
AGND
RD +
RD –
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
INT PWDN
/
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_
TRST
JTAG_TDI
1
2
3
4
5
6
7
8
9
10
11
38
39
40
41
42
43
44
45
46
47
48
35
34
33
32
31
30
29
28
27
26
25
23
22
21
20
19
18
17
16
15
14
13
PFBIN2
RX_CLK
RX_DV/MII_MODE
CRS/CRS_DV/LED_CFG
RX_ER/AMDIX_EN
COL/PHYAD0
RXD_0/PHYAD1
RXD_1/PHYAD2
RXD_2/PHYAD3
RXD_3/PHYAD4
IOGND
VDD_IO
24
37
36
12
RESET
TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
www.ti.com
2 Pin Descriptions
The TLK110 pins fall into the following interface categories (subsequent sections describe each interface):
• Serial Management Interface • Reset and Power Down
• MAC Data Interface • Bootstrap Configuration Inputs
• Clock Interface • 10/100Mbs PMD Interface
• LED Interface • Special Connect Pins
• JTAG Interface • Power and Ground pins
Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I Input Type: OD Open Drain
Type: O Output Type: PD, PU Internal Pulldown/Pullup
Type: I/O Input/Output Type: S Configuration Pin (All configuration pins have weak internal
pullups or pulldowns. Use an external 2.2kΩ resistor if you
need a different default value. See Section 3.1 for details.)
2.1 Pin Layout
Figure 2-1. TLK110 PIN DIAGRAM, TOP VIEW
This document describes signals that take on different names depending on configuration. In such cases,
the different names are placed together and separated by slash (/) characters. For example, "RXD_3 /
PHYAD4". Active low signals are represented by overbars.
.
4 Pin Descriptions Copyright © 2011–2014, Texas Instruments Incorporated
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