Datasheet

TLK110
www.ti.com SLLS901D –DECEMBER 2011–REVISED JANUARY 2014
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
1 Introduction .............................................. 1 5.1 100Base-TX Transmit Path ......................... 27
1.1 Features ............................................. 1 5.2 100Base-TX Receive Path ......................... 30
1.2 Applications .......................................... 1 5.3 10Base-T Receive Path ............................ 32
1.3 Device Overview ..................................... 2 5.4 Auto Negotiation .................................... 33
2 Pin Descriptions ......................................... 4 5.5 Link Down Functionality ............................ 35
2.1 Pin Layout ........................................... 4 6 Reset and Power Down Operation ................. 37
2.2 Serial Management Interface (SMI) ................. 5 6.1 Hardware Reset .................................... 37
2.3 MAC Data Interface .................................. 5 6.2 Software Reset ..................................... 37
2.4 10Mbs and 100Mbs PMD Interface .................. 6 6.3 Power Down/Interrupt .............................. 37
2.5 Clock Interface ....................................... 6 6.4 Power Save Modes ................................. 38
2.6 LED Interface ........................................ 6 7 Design Guidelines ..................................... 39
2.7 JTAG Interface ....................................... 6 7.1 TPI Network Circuit ................................. 39
2.8 Reset and Power Down ............................. 7 7.2 Clock In (XI) Requirements ......................... 39
2.9 Power and Bias Connections ........................ 7 8 Register Block ......................................... 41
3 Hardware Configuration ............................... 7 8.1 Register Definition .................................. 46
3.1 Bootstrap Configuration .............................. 8 8.2 Cable Diagnostic Control Register (CDCR) ........ 70
3.2 Power Supply Configuration ......................... 9 8.3 PHY Reset Control Register (PHYRCR) ........... 71
3.3 IO Pins Hi-Z State During Reset ................... 11 8.4 TX_CLK Phase Shift Register (TXCPSR) .......... 71
3.4 Auto-Negotiation .................................... 11 8.5 Power Back Off Control Register (PWRBOCR) .... 71
3.5 Auto-MDIX .......................................... 12 8.6 Voltage Regulator Control Register (VRCR) ....... 71
3.6 MII Isolate Mode .................................... 12 8.7 Cable Diagnostic Configuration/Result Registers .. 72
3.7 PHY Address ....................................... 12 9 Electrical Specifications ............................. 78
3.8 Software Strapping Mode .......................... 14 9.1 ABSOLUTE MAXIMUM RATINGS ................. 78
3.9 LED Interface ....................................... 16 9.2 RECOMMENDED OPERATING CONDITIONS .... 78
3.10 Loopback Functionality ............................. 17 9.3 48-Pin Industrial Device Thermal Characteristics .. 78
3.11 BIST ................................................ 19 9.4 DC CHARACTERISTICS, VDD_IO ................ 79
3.12 Cable Diagnostics .................................. 19 9.5 DC CHARACTERISTICS ........................... 79
4 Interfaces ................................................ 21 9.6 Power Supply Characteristics ...................... 80
4.1 Media Independent Interface (MII) ................. 21 9.7 AC Specifications ................................... 81
4.2 Reduced Media Independent Interface (RMII) ..... 22 Revision History ............................................ 96
4.3 Serial Management Interface ....................... 23 Revision History ............................................ 96
5 Architecture ............................................. 27
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