Datasheet

MDC
ZZ
MDIO
(STA)
TA
Register Data
Z
Z
0 1 0 00 00 00 00 0 00 01 00 00 0 0 00 01 1 0 00 1 0
Idle
Idle
Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
MDC
TA
Register Data
Z
Z
Z Z Z
0 0 0 00 00 00 00 0 00 00 00 00 0 00 01 1 1 11 1 1
Idle
Z
Z
MDIO
(STA)
MDIO
(PHY)
Idle Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used.
During power-up reset, the TLK110 latches the PHYAD[4:0] configuration pins (Pin 42 to Pin 46) to
determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To
maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is de-
asserted.
In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr
field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor
specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern.
This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is
defined as an idle bit time inserted between the Register Address field and the Data field. To avoid
contention during a read transaction, no device may actively drive the MDIO signal during the first bit of
Turnaround. The addressed TLK110 drives the MDIO with a zero for the second bit of turnaround and
follows this with the required data. Figure 4-3 shows the timing relationship between MDC and the MDIO
as driven/received by the Station (STA) and the TLK110 (PHY) for a typical register read access.
For write transactions, the station-management entity writes data to the addressed TLK110, thus
eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity
by inserting <10>. Figure 4-4 shows the timing relationship for a typical MII register write access. The
frame structure and general read/write transactions are shown in Table 4-2, Figure 4-3, and Figure 4-4.
Table 4-2. Typical MDIO Frame Format
MII Management Serial Protocol <idle><start><op code><device addr><reg addr><turnaround><data><idle>
Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Figure 4-3. Typical MDC/MDIO Read Operation
Figure 4-4. Typical MDC/MDIO Write Operation
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