Datasheet

PHY MAC
TXD[1:0]
TX_EN
TX_EN
TXD[1:0]
RX_ER (optional)
RXD[1:0]
RX_DV (optional)
RX_DV
RX_ER
RXD[1:0]
CRS/RX_DV
CRS/RX_DV
XI
50MHz
Clock Source
RX_CLK (optional)
RX_CLK
TLK110
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SLLS901D DECEMBER 2011REVISED JANUARY 2014
Figure 4-2 describes the RMII signals connectivity between the TLK110 and any MAC device.
Figure 4-2. TLK110 RMII/MAC Connection
RMII function includes a programmable elastic buffer to adjust for the frequency differences between the
reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal
propagation delay based on expected maximum packet size and clock accuracy.
Table 4-1 indicates how to program the buffer FIFO based on the expected max packet size and clock
accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same
accuracy.
Table 4-1. Recommended RMII Packet Sizes
Recommended packet size at Recommended packet size at
Start Threshold RBR[1:0] Latency Tolerance
±50ppm ±100ppm
1(4-bits) 2 bits 2400 bytes 1200 bytes
2(8-bits) 6 bits 7200 bytes 3600 bytes
3(12-bits) 10 bits 12000 bytes 6000 bytes
0(16-bits) 14 bits 16800 bytes 8400 bytes
4.3 Serial Management Interface
The Serial Management Interface (SMI), provides access to the TLK110 internal register space for status
information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented
register set consists of all the registers required by the IEEE802.3-2002, plus several others to provide
additional visibility and controllability of the TLK110 device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock
is sourced by the external management entity, also called Station (STA), and can run at a maximum clock
rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management
entity when the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is
latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2k Ω) which,
during IDLE and turnaround, pulls MDIO high.
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