Datasheet

TLK110

SLLS901D –DECEMBER 2011–REVISED JANUARY 2014

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3.5 Auto-MDIX

The TLK110 device automatically determines whether or not it needs to cross over between pairs,

eliminating the requirement for an external crossover cable. If the TLK110 interoperates with a device that

implements MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 determines which

device performs the crossover.

Auto-MDIX is enabled by default and can be configured via pin strap, SW Strap register SWSCR1

(0x09h), bit 14 or via register PHYCR (0x19h), bit 15.

The crossover can be manually forced through bit 14 of the PHYCR (0x19h) register. Neither Auto-

Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs.

Auto-MDIX can be used in the forced 100Base-TX mode. Because in modern networks all the nodes are

100Base-TX, having the Auto-MDIX working in the forced 100Base-TX mode resolves the link faster

without the need for the long Auto-Negotiation period.

3.6 MII Isolate Mode

The TLK110 can be put into MII-Isolate mode by writing bit 10 of the BMCR register.

When in the MII-Isolate mode, the TLK110 ignores packet data present at the TXD[3:0], TX_EN inputs,

and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS

outputs. When in isolate mode, the TLK110 continues to respond to all management transactions.

When in isolate mode, the PMD output pair does not transmit packet data, but continues to source

100Base-TX scrambled idles or 10Base-T normal link pulses. The TLK110 can auto-negotiate or parallel

detect on the receive signal at the PMD input pair. A valid link can be established for the receiver even

when the TLK110 is in Isolate mode.

3.7 PHY Address

The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown in Table 3-2.

Table 3-2. PHY Address Mapping

PIN Number PHYAD FUNCTION RXD FUNCTION

42 PHYAD0 COL

43 PHYAD1 RXD_0

44 PHYAD2 RXD_1

45 PHYAD3 RXD_2

46 PHYAD4 RXD_3

Each TLK110 or port sharing an MDIO bus in a system must have a unique physical address. With 5

address input pins, the TLK110 can support PHY Address values 0 (<00000>) through 31 (<11111>). The

address-pin states are latched into an internal register at device power-up and hardware reset. Because

all the PHYAD[4:0] pins have weak internal pull-down/up resistors, the default setting for the PHY address

is 00001 (0x01h).

See Figure 3-3 for an example of a PHYAD connection to external components. In this example, the

PHYAD configuration results in address 00011 (0x03h).

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