Datasheet

Pin 13
(RD–)
RD–
Pin 14
(RD+)
RD+
49.9 W
3.3V
Supply
Pin 16
(TD–)
TD–
Pin 17
(TD+)
TD+
1:1
T1
RJ45
Pin 22
(AVDD33)
Pin 23
(PFBOUT)
Pin 18
(PFBIN1)
Pin 37
(PFBIN2)
3.3V
Supply
Pin 32
(VDD_IO)
Pin 48
(VDD_IO)
1.55V
1.55V
Supply
Supply
Floating
49.9 W
49.9 W
49.9 W
1:1
IO Supply
10 Fm10nF1nF100pF
10 Fm10nF1nF100pF
10 Fm
10 Fm
10nF
10nF
1nF
1nF
100pF
100pF
10 Fm 10nF 1nF 100pF
0.1 F*m
1 Fm
0.1 F*m
1 Fm
0.1 Fm
0.1 Fm
3.3V
Supply
3.3V
Supply
1 Fm
1 Fm
TLK110
SLLS901D –DECEMBER 2011–REVISED JANUARY 2014 www.ti.com
3.2.2 Dual Supply Operation
When a 1.55V external power rail is available, the TLK110 can be configured as shown in Figure 3-2.
PFBOUT (pin 23) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 18) and PFBIN2
(pin 37). Furthermore, to lower the power consumption, the internal regulator should be powered down by
writing ‘1’ to bit 15 of the VRCR register (0x00d0h).
Figure 3-2. Power Connections for Dual Supply Operation
When operating with dual supplies, follow these guidelines:
• When powering up, ramp up the 3.3V supply before the 1.55V supply.
• When powering down, turn off the 1.55V supply before turning off the 3.3V supply.
• Use the external RESET pin after power up to reset the PHY.
• To use the internal power-on reset, PFBIN1 and PFBIN2 must be operational less than 100ms after
3.3V rises to detect the internal RESET.
3.2.3 Variable IO Voltage
The TLK110 digital IO pins can operate with a variable supply voltage. While the primary applications will
use 3.3V, VDD_IO can also operate on 2.5V, and for MII mode only, VDD_IO of 1.8V can be used as well.
For more details, see Section 9.4.
10 Hardware Configuration Copyright © 2011–2014, Texas Instruments Incorporated
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