TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver Check for Samples: TLK110 1 Introduction 1.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 1.3 www.ti.com Device Overview The TLK110 is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling. This device integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. The TLK110 supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Media Access Controller (MAC).
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 2 Pin Descriptions The TLK110 pins fall into the following interface categories (subsequent sections describe each interface): • • • • • Serial Management Interface MAC Data Interface Clock Interface LED Interface JTAG Interface • • • • • Reset and Power Down Bootstrap Configuration Inputs 10/100Mbs PMD Interface Special Connect Pins Power and Ground pins Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
TLK110 www.ti.com 2.2 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Serial Management Interface (SMI) PIN NAME NO. TYPE DESCRIPTION MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The maximum MDC rate is 25MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the TX_CLK or the RX_CLK. MDC 31 I MDIO 30 I/O 2.3 MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 2.4 www.ti.com 10Mbs and 100Mbs PMD Interface PIN NAME TYPE NO. DESCRIPTION Differential common driver transmit output (PMD Output Pair): These differential outputs are automatically configured to either 10Base-T or 100Base-TX signaling. TD–, TD+ 16, 17 I/O In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 PIN NAME NO. TYPE DESCRIPTION JTAG_TMS 10 I, PU JTAG Test Mode Select: This pin has a weak internal pullup. JTAG_TRST 11 I, PU JTAG Reset: This pin is an active-low asynchronous test reset with a weak internal pullup. 2.8 Reset and Power Down PIN NAME NO. RESET 29 TYPE I, PU DESCRIPTION This pin is an active-low reset input that initializes or re-initializes all the internal registers of the TLK110.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 3.1 www.ti.com Bootstrap Configuration Bootstrap configuration is a convenient way to configure the TLK110 into specific modes of operation. Some of the functional pins are used as configuration inputs. The logic states of these pins are sampled during reset and are used to configure the device into specific modes of operation. The table below describes bootstrap configuration. A 2.
TLK110 www.ti.com 3.2 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Power Supply Configuration The TLK110 provides best-in-class flexibility of power supplies. 3.2.1 Single Supply Operation If a single 3.3V power supply is desired, the TLK110 internal regulator provides the necessary core supply voltages. Ceramic capacitors of 10µf and 0.1µf should be placed close to the PFBOUT (pin 23) which is the output of the internal regulator.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 3.2.2 www.ti.com Dual Supply Operation When a 1.55V external power rail is available, the TLK110 can be configured as shown in Figure 3-2. PFBOUT (pin 23) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 18) and PFBIN2 (pin 37). Furthermore, to lower the power consumption, the internal regulator should be powered down by writing ‘1’ to bit 15 of the VRCR register (0x00d0h). 3.3V Supply 10mF 3.
TLK110 www.ti.com 3.3 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 IO Pins Hi-Z State During Reset The following IO or output pins are in hi-Z state when RESET is active (Low). Type Internal PU/PD Type Internal PU/PD TXD_3 IO PD TX_EN IO PD RX_ER IO PU COL IO INT/PWDN IO PU PU RXD_0 IO PD LED_ACT LED_SPEED IO PU RXD_1 IO PD IO PU RXD_2 IO PD LED_LINK IO PU RXD_3 IO PD MDIO IO TX_CLK O RX_DV IO PD CLK25MHz_OUT O CRS IO PU RX_CLK O Pin Name 3.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 3.5 www.ti.com Auto-MDIX The TLK110 device automatically determines whether or not it needs to cross over between pairs, eliminating the requirement for an external crossover cable. If the TLK110 interoperates with a device that implements MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 determines which device performs the crossover.
TLK110 PHYAD3 = 0 PHYAD2 = 0 COL RXD_0 RXD_3 PHYAD4 = 0 RXD_1 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 RXD_2 www.ti.com PHYAD1 = 1 PHYAD0 = 1 2.2 kW VCC Figure 3-3.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 3.8 www.ti.com Software Strapping Mode The TLK110 provides a mechanism to extend the number of configuration pins to allow wider system programmability of PHY functions. Connecting an external pull-down to pin 21 causes the device to enter SW Strapping Mode after power-up or a hardware reset event. In this mode the device wakes up after power-up/hardware reset in power down mode.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Figure 3-5 shows the timing relationship for typical SW Strapping programming. SW_STRAP HW_RESET Config_Done 200 ms MDIO PHY State Write/Read Transactions Reset Power Down Wake up Try to establish Link Figure 3-5. TLK110 SW Strap Timing Diagram Connecting an external pull-up resistor to pin 21 disables Software Strapping Mode during power up or HW Reset.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 3.9 www.ti.com LED Interface The TLK110 supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configurations: Link, Speed, and Activity. Functions are multiplexed among the LEDs into three modes. The LEDs can be controlled by configuration pin and-or internal register bits. Bits 6:5 of the PHY Control register (PHYCR) selects the LED mode as described in Table 3-3. Table 3-3.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 3.10 Loopback Functionality The TLK110 provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK110 digital and analog data path. Generally, the TLK110 may be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback. 3.10.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 3.10.2 www.ti.com Far-End Loopback Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In this mode, data that is received from the link partner passes through the PHY's receiver, looped back on the MII and transmitted back to the link partner. Figure 3-8 shows Far-end loopback functionality.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 3.11 BIST The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST can be performed using both internal loopback (digital or analog) or external loopback using a cable fixture.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com For all TDR measurements, the transformation between time of arrival and physical distance is done by the external host using minor computations (such as multiplication, addition and lookup tables). The host must know the expected propagation delay of the cable, which depends, among other things, on the cable category (for example, CAT5, CAT5e, or CAT6).
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 4 Interfaces 4.1 Media Independent Interface (MII) The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22. The MII signals are summarized below.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 4.2 www.ti.com Reduced Media Independent Interface (RMII) TLK110 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u MII as specified in Clause 22.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Figure 4-2 describes the RMII signals connectivity between the TLK110 and any MAC device. PHY TX_EN TXD[1:0] MAC TX_EN TXD[1:0] RX_CLK RX_CLK (optional) RX_DV RX_DV (optional) RX_ER RX_ER (optional) RXD[1:0] CRS/RX_DV RXD[1:0] CRS/RX_DV XI 50MHz Clock Source Figure 4-2.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During power-up reset, the TLK110 latches the PHYAD[4:0] configuration pins (Pin 42 to Pin 46) to determine its address. The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted.
TLK110 www.ti.com 4.3.1 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Extended Address Space Access The TLK110 SMI function supports read/write access to the extended register set using registers REGCR(0x000Dh) and ADDAR(0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in IEEE802.3ah Draft for clause 22 for accessing the clause 45 extended register set.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 4.3.1.3 To 1. 2. 3. 4. www.ti.com Write (no post increment) Operation write a register in the extended register set: Write the value 0x001F (address function field = 00, DEVAD = 31) to register REGCR. Write the desired register address to register ADDAR. Write the value 0x401F (data, no post increment function field = 01, DEVAD = 31) to register REGCR. Write the content of the desired extended register set register to register ADDAR.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 5 Architecture The TLK110 Fast Ethernet transceiver is a physical layer core for Ethernet 100Base-TX and 10Base-T applications. The TLK110 contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT 3 and 5 unshielded twisted pair. The core supports the IEEE 802.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com TX_CLK TX_EN TXD[3:0] Data n-2 [3:0] Data n-2 [7:4] Data n-1 [3:0] Data n-1 [7:4] Data n [3:0] Data n [7:4] Error Code RX_CLK RX_DV RXD[3:0] Data n-2 [3:0] Data n-2 [7:4] Data n-1 [3:0] Data n-1 [7:4] Data n [3:0] Data n [7:4] Error Code Don't Care RX_ER Figure 5-2. Transmit Code Error Forwarding Diagram 5.1.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 5-1.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 5.1.5 www.ti.com Digital to Analog Converter The multipurpose programmable transmit Digital to Analog Converter (DAC) receives digital coded symbols and generates filtered analog symbols to be transmitted on the line. In 100B-TX the DAC applies a low-pass shaping filter to minimize EMI. The DAC is designed to improve the return loss requirements and enable the use of low-cost transformers.
TLK110 www.ti.com 5.2.5 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Descrambler The descrambler is used to descramble the received NRZ data. The data is further deserialized and the parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the 100BTX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During that time, neither data transmission nor reception is enabled.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 5.2.10 Signal Detect The signal detect function of the TLK110 is incorporated to meet the specifications mandated by the ANSIFDDI TP-PMD Standard as well as the IEEE 802.3 100Base-TX Standard for both voltage thresholds and timing parameters. The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an IIR filter, this robust energy detector has excellent reaction time and reliability.
TLK110 www.ti.com 5.3.4 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Jabber Function Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition. The jabber function monitors the TLK110 output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 100ms.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com When auto negotiation has started, the TLK110 transmits FLP on one twisted pair and listens on the other, thus trying to find out whether the other link partner supports the auto negotiation function as well. The decision on what pair to transmit/listen depends on the MDI/MDI-X state. If the other link partner activates auto negotiation, then the two parties begin to exchange their information.
TLK110 www.ti.com 5.4.4 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Next Page Support The TLK110 supports the optional feature of the transmission and reception of auto-negotiation additional (vendor specific) next pages. If next pages are needed, the user must set register ANAR(0x0004h) bit 15 to '1'. The next pages are then sent and received through registers ANNPTR(0x0007h) and ANLNPTR(0x0008h), respectively.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com The Fast Link Down functionality allows the use of each of these options separately or in any combination. Note that since this mode enables extremely quick reaction time, it is more exposed to temporary bad linkquality scenarios.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 6 Reset and Power Down Operation The TLK110 includes an internal power-on-reset (POR) function, and therefore does not need an explicit reset for normal operation after power up. At power-up, if required by the system, the RESET pin (active low) should be de-asserted 200µs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 6.4 www.ti.com Power Save Modes The TLK110 supports three types of power-save modes. The lowest power consumption is achieved in IEEE power down mode. To enter IEEE power down mode, pull the INT/PWDN pin to LOW or program bit 11 in the Basic Mode Control Register (BMCR), address 0x0000. In this mode all internal circuitry except SMI functionality is shut down (Register access is still available).
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 7 Design Guidelines 7.1 TPI Network Circuit Figure 7-1 shows the recommended circuit for a 10/100Mbs twisted pair interface. Below is a partial list of recommended transformers. Variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application. • • Pulse H1102 Pulse HX1198 Vdd Common-mode chokes may be required. RD– 49.9 W Vdd 1:1 0.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 7.2.2 www.ti.com Crystal The use of a 25MHz, parallel, 20pF-load crystal is recommended if a crystal source is desired. Figure 7-2 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel-resonance AT-cut crystal with a minimum drive level of 100μW and a maximum of 500μW.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8 Register Block Table 8-1.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com Table 8-1.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-2.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com Table 8-2.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-3.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.1 www.ti.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-4. Basic Mode Control Register (BMCR), address 0x0000 (continued) BIT 11 BIT NAME IEEE Power Down DEFAULT 0, RW DESCRIPTION Power Down: 1 = Enables IEEE power down mode 0 = Normal operation Setting this bit powers down the PHY. Only minimal register functionality is enabled during the power down condition. To control the power down mechanism, this bit is ORed with the input from the INT/PWDN pin.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.1.2 www.ti.com Basic Mode Status Register (BMSR) Table 8-5. Basic Mode Status Register (BMSR), address 0x0001 BIT BIT NAME DEFAULT 15 100Base-T4 0, RO/P 14 100Base-TX Full Duplex 1, RO/P 100Base-TX Half Duplex 1, RO/P 10Base-T Full Duplex 1, RO/P 10Base-T Half Duplex 1, RO/P DESCRIPTION 100Base-T4 Capable: This protocol is not available. Always 0 = Device does not perform 100Base-T4 mode.
TLK110 www.ti.com 8.1.3 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 PHY Identifier Register 1 (PHYIDR1) The PHY Identifier Registers 1 and 2 together form a unique identifier for the TLK110. The identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.1.5 www.ti.com Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they are transmitted to its link partner during Auto-Negotiation. Table 8-8.
TLK110 www.ti.com 8.1.6 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 8-9.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.1.7 www.ti.com Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 8-10. Auto-Negotiate Expansion Register (ANER), address 0x0006 BIT BIT NAME 15:5 RESERVED 4 PDF DEFAULT DESCRIPTION 0, RO RESERVED: Writes ignored, Read as 0.
TLK110 www.ti.com 8.1.8 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Auto-Negotiate Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 8-11.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.1.9 www.ti.com Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 8-12.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.1.10 Software Strap Control register 1 (SWSCR1) This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com Table 8-13. SW Strap Control register 1 (SWSCR1), address 0x0009 (continued) BIT 9 BIT NAME RMII Enhanced Mode DEFAULT 0, SWS, RW DESCRIPTION RMII Enhanced Mode: 1 = Enable RMII Enhanced Mode 0 = RMII operates in normal mode In normal mode, If the line is not idle CRS_DV goes high. As soon as the False Carrier is detected, RX_ER is asserted and RXD is set to “2”. This situation remains for the duration of the receive event.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-13. SW Strap Control register 1 (SWSCR1), address 0x0009 (continued) BIT BIT NAME 3:2 Fast AN Sel DEFAULT 0, SWS, RW DESCRIPTION Fast Auto-Negotiation Select bits: Fast AN Select Break Link Timer Link Fail Inhibit Timer Auto-Neg Wait Timer <00> 80 50 35 <01> 120 75 50 <10> 240 150 100 <11> NA NA NA Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 8.1.11 Software Strap Control register 2 (SWSCR2) This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.1.12 Software Strap Control Register 3 (SWSCR3) This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 8.1.13.1 Register Control Register (REGCR) This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate MMD. REGCR also contains selection bits for auto increment of the data register. This register contains the device address to be written to access the extended registers.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-18. PHY Status Register (PHYSTS), address 0x0010 (continued) BIT NAME DEFAULT DESCRIPTION This bit will be cleared upon a read of the FCSR register.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com Table 8-18.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-19. PHY Specific Control Register (PHYSCR), address 0x0011 (continued) BIT NAME DEFAULT DESCRIPTION 11 Scrambler Bypass 0,RW 10 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com Table 8-20. MII Interrupt Status Register 1 (MISR1), address 0x0012 (continued) BIT DEFAULT DESCRIPTION 11 Duplex Mode Changed INT NAME 0,RO, COR Change of duplex status interrupt: 1 = Duplex status change interrupt is pending 0 = No change of duplex status 10 Auto-Negotiation Completed INT 0,RO, COR Auto-Negotiation Complete interrupt: 1 = Auto-negotiation complete interrupt is pending.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-21.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 8.1.20 BIST Control Register (BISCR) This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register. Table 8-24.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.1.21 RMII Control and Status Register (RCSR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 8-25. RMII Control and Status Register (RCSR), address 0x0017 NAME DEFAULT 15:6 RESERVED BIT 0000 0000 00, RO RESERVED: Writes ignored, read as 0.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 8.1.22 LED Control Register (LEDCR) This register provides the ability to directly manually control any or all LED outputs. Table 8-26. LED Control Register (LEDCR), address 0x0018 NAME DEFAULT DESCRIPTION 15:11 BIT RESERVED 0000 0, ro RESERVED: Writes ignored, read as 0.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-27. PHY Control Register (PHYCR), address 0x0019 (continued) BIT NAME DEFAULT 11 MI Link Status 0, RO MII Link Status: 1 = 100BT Full-duplex Link is active and it was established using Auto-Negotiation 0 = No active link of 100BT Full-duplex, established using Auto-Negotiation 10:8 RESERVED 000, RO RESERVED: Writes ignored, read as 0.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 8.1.25 BIST Control and Status Register 1 (BICSR1) This register provides the total number of error bytes that was received by the PRBS checker and defines the Inter packet Gap (IPG) for the packet generator. Table 8-29.
TLK110 www.ti.com 8.3 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 PHY Reset Control Register (PHYRCR) Table 8-32. PHY Reset Control Register (PHYRCR), address 0x001F BIT NAME DEFAULT FUNCTION 15 Software Reset 0, RW,SC Software Reset: 1 = Reset PHY. This bit is self cleared and has same effect as Hardware reset pin. 0 = Normal Operation 14 Software Restart 0, RW,SC Software Restart: 1 = Reset PHY. This bit is self cleared and resets all PHY circuitry except the registers.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com Table 8-35. Voltage Regulator Control Register (VRCR), address 0x00D0 BIT NAME DEFAULT FUNCTION 15 VRPD 0, RW, SC Voltage Regulator Power Down: 1 = Power Down. Allow the system to power down the voltage regulator block of the PHY using register access. 0 = Normal Operation. Voltage Regulator is powered and outputs voltage on the PFBOUT pin. 14:4 RESERVED 000 0000 0000, RW RESERVED: Must be written as 0.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-37. Cable Diagnostic Specific Control Register (CDSCR), address 0x0170 (continued) BIT 7:0 BIT NAME DEFAULT RESERVED 0, RO DESCRIPTION RESERVED: Writes ignored, read as 0. Table 8-38.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 8.7.5 www.ti.com Cable Diagnostic Location Results Register 3 (DDLRR3) This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-43.
TLK110 www.ti.com 8.7.9 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Cable Diagnostic Amplitude Results Register 2 (CDARR2) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-47. Cable Diagnostic Amplitude Results Register 2 (CDARR2), address 0x0186 BIT NAME DEFAULT FUNCTION 15 RESERVED 0,RO RESERVED: Writes ignored, read as 0.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 8.7.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4) This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E). Table 8-49. Cable Diagnostic Amplitude Results Register 4 (CDARR4), address 0x0188 BIT NAME DEFAULT FUNCTION 15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 Table 8-51. Cable Diagnostic General Results Register (CDGRR), address 0x018A (continued) BIT NAME DEFAULT FUNCTION 3 Above 5 TPTD Peaks 0, RO More than 5 reflections were detected on TPTD 2 Above 5 TPRD Peaks 0, RO More than 5 reflections were detected on TPRD RESERVED 00, RO RESERVED: Writes ignored, read as 0 1:0 8.7.14 ALCD Control and Results 2 (ALCDRR2) Table 8-52.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 9 Electrical Specifications All parameters are derived by test, statistical analysis, or design. ABSOLUTE MAXIMUM RATINGS (1) 9.1 VDD_IO, AVDD33 Supply voltage PFBIN1, PFBIN2 DC Input voltage –0.3 to 3.8 XO DC Output voltage –0.3 to 3.8 Other outputs V –0.3 to 3.8 TJ Maximum die temperature TS Storage Temperature Human-Body Model ESD Charged-Device Model 9.2 V –0.3 to 6 Other Inputs (4) V –0.3 to 3.
TLK110 www.ti.com 9.4 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 DC CHARACTERISTICS, VDD_IO over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3.3V VDD_IO VIH Input high voltage VIL Input low voltage VOL Output low voltage VOH Output high voltage Nominal VCC = 3.3V VDD_IO = 3.3V ±10% 2.0 V VDD_IO = 3.3V±10% 0.8 V IOL = 4 mA VDD_IO = 3.3V±10% 0.4 V IOH = –4 mA VDD_IO = 3.3V±10% VDD_IO – 0.5 V VDD_IO = 2.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.6 www.ti.com Power Supply Characteristics The data was measured using a TLK110 evaluation board. The current from each of the power supplies is measured and the power dissipation is computed. For the single 3.3V external supply case the power dissipation across the internal linear regulator is also included. All the power dissipation numbers are measured at the nominal power supply and typical temperature of 25°C.
TLK110 www.ti.com 9.7 9.7.1 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 AC Specifications Power Up Timing Table 9-1. Power Up Timing PARAMETER t1 TEST CONDITIONS Time from powerup to hardware-configuration pin transition to output-driver function, using internal POR (RESET pin tied high) MIN TYP MAX 100 270 UNIT ms VDD Hardware RESET t1 Dual function pins Become enabled As outputs Figure 9-1.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.7.3 www.ti.com MII Serial Management Timing Table 9-3. MII Serial Management Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 2.5 25 MHz 30 ns t1 MDC Frequency t2 MDC to MDIO (Output) Delay Time t3 MDIO (Input) to MDC Hold Time 10 ns t4 MDIO (Input) to MDC Setup Time 10 ns 0 MDC t1 t2 MDIO (Output) MDC t3 t4 MDIO (Input) Valid Data T0340-01 Figure 9-3. MII Serial Management Timing 9.7.
TLK110 www.ti.com 9.7.5 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 100Mb/s MII Receive Timing Table 9-5. 100Mb/s MII Receive Timing PARAMETER (1) TEST CONDITIONS t1 RX_CLK High Time t2 RX_CLK Low Time t3 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay (1) MIN TYP MAX UNIT 100Mbs Normal mode 16 20 24 ns 100Mbs Normal mode 10 30 ns RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.7.7 www.ti.com 100Base-TX Transmit Packet Deassertion Timing Table 9-7. 100Base-TX Transmit Packet Deassertion Timing PARAMETER t1 TEST CONDITIONS TX_CLK to PMD Output Pair deassertion MIN 100Mbs Normal mode TYP 4.6 MAX UNIT bits TX_CLK TX_EN TXD t1 PMD Output Pair DATA DATA (T/R) (T/R) IDLE IDLE T0344-01 Figure 9-7.
TLK110 www.ti.com 9.7.8 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 100Base-TX Transmit Timing (tR/F and Jitter) Table 9-8. 100Base-TX Transmit Timing (tR/F and Jitter) PARAMETER t1 t2 (1) (2) TEST CONDITIONS MIN TYP MAX 3 4 5 ns 100Mbs tR and tF Mismatch (2) 500 ps 100Mbs PMD Output Pair Transmit Jitter 1.4 ns 100Mbs PMD Output Pair tR and tF (1) UNIT Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.7.9 www.ti.com 100Base-TX Receive Packet Latency Timing Table 9-9.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.7.11 10Mbs MII Transmit Timing Table 9-11. 10Mbs MII Transmit Timing PARAMETER MIN TYP MAX UNIT 10Mbs MII mode 190 200 210 ns TXD[3:0], TX_EN Data Setup to TX_CLK ↑ 10Mbs MII mode 25 ns TXD[3:0], TX_EN Data Hold from TX_CLK ↑ 10Mbs MII mode 0 ns t1 TX_CLK Low Time t2 TX_CLK High Time t3 t4 TEST CONDITIONS An attached Mac should drive the transmit signals using the positive edge of TX_CLK.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 9.7.13 10Base-T Transmit Timing (Start of Packet) Table 9-13. 10Base-T Transmit Timing (Start of Packet) PARAMETER t1 (1) TEST CONDITIONS Transmit Output Delay from the Falling Edge of TX_CLK MIN 10Mbs MII mode TYP MAX 5.8 UNIT (1) bits (1) 1 bit time = 100ns in 10Mb/s. TX_CLK TX_EN TXD t1 PMD Output Pair Figure 9-13. 10Base-T Transmit Timing (Start of Packet) 9.7.14 10Base-T Transmit Timing (End of Packet) Table 9-14.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.7.15 10Base-T Receive Timing (Start of Packet) Table 9-15.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 9.7.17 10Mb/s Jabber Timing Table 9-17. 10Mb/s Jabber Timing PARAMETER t1 Jabber Activation Time t2 Jabber Deactivation Time TEST CONDITIONS MIN TYP MAX 100 10 Mb/s MII mode UNIT ms 500 TX_EN t1 PMD Output Pair t2 COL Figure 9-17. 10Mb/s Jabber Timing 9.7.18 10Base-T Normal Link Pulse Timing Table 9-18.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.7.19 Auto-Negotiation Fast Link Pulse (FLP) Timing Table 9-19.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 9.7.21 100Mbs Loopback Timing Table 9-21.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.7.22 10Mbs Internal Loopback Timing Table 9-22. 10Mbs Internal Loopback Timing PARAMETER t1 TEST CONDITIONS TX_EN to RX_DV Loopback MIN TYP 10Mbs internal loopback mode MAX UNIT μs 1.7 TX_CLK TX_EN TXD[3:0] CRS t1 RX_CLK RX_DV RXD[3:0] T0362-01 (1) (2) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. Analog loopback was used. Looping the TX to RX at the analog input/output stage.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com 9.7.24 RMII Receive Timing Table 9-24. RMII Receive Timing PARAMETER TEST CONDITIONS MIN XI Clock Period t2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from XI rising t3 CRS ON delay From JK symbol on PMD Receive Pair to initial assertion of CRS_DV 17.6 t4 CRS OFF delay From TR symbol on PMD Receive Pair to initial assertion of CRS_DV 26.2 t5 RXD[1:0] and RX_ER latency From symbol on Receive Pair.
TLK110 www.ti.com SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 9.7.25 Isolation Timing Table 9-25. Isolation Timing PARAMETER t1 TEST CONDITIONS MIN TYP MAX From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 71 UNIT ns H/W or S/W Reset t1 ISOLATE MODE NORMAL T0365-01 Figure 9-25. Isolation Timing 9.7.26 25MHz_OUT Clock Timing Table 9-26.
TLK110 SLLS901D – DECEMBER 2011 – REVISED JANUARY 2014 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (October 2012) to Revision C • • • • • • Page Added bullet item "Variable I/O voltage range: 1.8V to 3.3V" .................................................................. 1 Updated to include variable IO capability - changed signal name "VDD33_IO" to "VDD_IO" .............................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE MATERIALS INFORMATION www.ti.com 23-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLK110PTR Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.9 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 23-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK110PTR LQFP PT 48 1000 333.2 345.9 28.
MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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