Datasheet

Pin 9
(RD–)
RD–
Pin 10
(RD+)
RD+
49.9 W
3.3V
Supply
Pin 11
(TD–)
TD–
Pin 12
(TD+)
TD+
1:1
T1
RJ45
Pin 14
(AVDD33)
Pin 15
(PFBOUT)
Pin 13
(PFBIN1)
Pin 24
(PFBIN2)
3.3V
Supply
Pin 21
(VDD33_IO)
Floating
49.9 W
49.9 W
49.9 W
1:1
3.3V
Supply
10 Fm10nF1nF100pF
1.55V
Supply
10 Fm 10nF 1nF 100pF
10 Fm 10nF 1nF 100pF
0.1 F*m
1 Fm
0.1 F*m
1 Fm
0.1 Fm
0.1 Fm
3.3V
Supply
3.3V
Supply
1 Fm
1 Fm
1.55V
Supply
10 Fm 10nF 1nF 100pF
TLK105
TLK106
www.ti.com SLLSEB8A –AUGUST 2012–REVISED MARCH 2013
3.2.2 Dual Supply Operation
When a 1.55V external power rail is available, the TLK10x can be configured as shown in Figure 3-2.
PFBOUT (pin 15) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 13) and PFBIN2
(pin 24). Furthermore, to lower the power consumption, the internal regulator should be powered down by
writing ‘1’ to bit 15 of the VRCR register (0x00d0h).
Figure 3-2. Power Connections for Dual Supply Operation
When operating with dual supplies, follow these guidelines:
• When powering up, ramp up the 3.3V supply before the 1.55V supply.
• When powering down, turn off the 1.55V supply before turning off the 3.3V supply.
• Use the external RESET pin after power up to reset the PHY.
• To use the internal power-on reset, PFBIN1 and PBIN2 must be operational less than 100ms after
3.3V rises to detect the internal RESET.
3.3 IO Pins Hi-Z State During Reset
The following IO or output pins are in hi-Z state when RESET is active (Low).
Internal Internal
Pin Name Type Pin Name Type
PU/PD PU/PD
TXD_3 IO PD COL IO PU
TX_EN IO PD RXD_0 IO PD
INT/PWDN IO PU RXD_1 IO PD
LED_LINK IO PU RXD_2 IO PD
MDIO IO RXD_3 IO PD
RX_DV IO PD TX_CLK O
CRS IO PU CLK25MHz_OUT O
RX_ER IO PU RX_CLK O
Copyright © 2012–2013, Texas Instruments Incorporated Hardware Configuration 9
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