Datasheet

PMDInputPair
SD+Intermal
T0360-01
t
1
t
2
TLK105
TLK106
SLLSEB8A –AUGUST 2012–REVISED MARCH 2013 www.ti.com
9.6.20 100Base-TX Signal Detect Timing
Table 9-20. 100Base-TX Signal Detect Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
SD Internal Turn-on Time 100 μs
t
2
Internal Turn-off Time 200 μs
NOTE: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
Figure 9-20. 100Base-TX Signal Detect Timing
9.6.21 100Mbs Loopback Timing
Table 9-21. 100Mbs Loopback Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
100Mbs external loopback 241 242 243
100Mbs external loopback – fast RX_DV mode 201 202 203
t
1
TX_EN to RX_DV Loopback 100Mbs analog loopback 232 233 234 ns
100Mbs PCS Input loop back 120 121 122
100Mbs MII loop back 8 9 10
88 Electrical Specifications Copyright © 2012–2013, Texas Instruments Incorporated
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